ARMv8-M refers to the latest architecture version of the Cortex-M series of 32-bit microcontrollers designed by ARM. It builds upon previous versions like ARMv6-M and ARMv7-M by adding support for newer features like TrustZone for Cortex-M and v8-M Security Extensions.
Background on ARM Cortex-M Series
The Cortex-M series is ARM’s range of 32-bit microcontroller cores. They are designed for embedded and IoT applications requiring real-time responsiveness, low cost, and low power consumption. The Cortex-M cores are simpler than the Cortex-A series used in mobile SoCs but still include advanced features like Thumb-2 instruction set, NVIC interrupt controller, and optional FPU.
Some key attributes of Cortex-M cores:
- 32-bit RISC architecture
- Thumb-2 instruction set for improved code density
- Up to 16 priority levels in NVIC interrupt controller
- Integrated sleep modes for low power
- Memory Protection Unit (MPU) for security
- Tightly-coupled memories for deterministic real-time performance
The Cortex-M series is split into three main groups based on increasing performance and capabilities:
- Cortex-M0/M0+ – Ultra low power IoT endpoints
- Cortex-M3/M4/M7 – Feature-rich MCUs for industrial, auto, and consumer apps
- Cortex-M23/M33 – Microcontrollers with DSP capabilities
History of Cortex-M Architectures
ARM has iterated on the Cortex-M architecture over the years, with each version adding new features:
- ARMv6-M – Initial version supporting Thumb-2, NVIC, and optional FPU
- ARMv7-M – Added more Thumb-2 instructions, enhanced debug, and more MPU regions
- ARMv8-M Baseline – Mandatory MPU, improved exception model, more debugging features
- ARMv8-M Mainline – Additional features like TrustZone for Cortex-M and Branch Target Identification (BTI)
The ARMv6-M and ARMv7-M architectures target all Cortex-M cores. ARMv8-M is split into Baseline and Mainline versions, with Baseline targeting the Cortex-M0/M0+/M1 and Mainline targeting Cortex-M23 and above.
ARMv8-M Main Features
Let’s look at some of the major features introduced in ARMv8-M for Cortex-M cores:
TrustZone for Cortex-M
TrustZone divides the processor into secure and non-secure states. The secure state has full access while the non-secure state can only access permitted resources. This allows isolation of critical code and data like cryptography keys.
Cortex-M23 and M33 cores have TrustZone support. The MPU and system control registers determine which memory regions are accessible in non-secure state.
v8-M Security Extensions
Building on TrustZone, the v8-M Security Extensions add additional hardware security capabilities like:
- Secure state debugging disable
- Cryptography extensions
- Random number generator
- Hardware entropy source
- True random number generator
This improves security for technologies like secure boot, authentication, encryption, and anti-tampering.
New Instruction Set Extensions
ARMv8-M expands the Thumb-2 instruction set with new instructions for DSP and floating point acceleration. These include:
- Half-precision floating point (FP16)
- Single instruction, multiple data (SIMD)
- Saturated math operations
- Bitfield manipulation
- Hardware division for Cortex-M cores without FPU
The additional DSP instructions boost performance for applications like machine learning, audio processing, and computer vision.
Enhanced Memory Protection Unit (MPU)
The MPU defines memory access permissions in Cortex-M cores. ARMv8-M makes the MPU mandatory and increases minimum region count from 8 to 12.
MPU enhancements provide finer-grained control over memory access rights. This improves security for multithreaded apps and防止外部代码/数据损坏其他模块。
Improved Debugging and Tracing
ARMv8-M includes several improvements for debugging and tracing complex software on Cortex-M cores, such as:
- More breakpoints and watchpoints
- Cross-triggering to link events to actions
- Embedded Trace Macrocell (ETM) upgrades
- Profiling counters
- Support for third-party trace IPs
These features help accelerate testing and certification of safety-critical designs.
New Exception and Interrupt Model
The exception and interrupt handling model is upgraded in ARMv8-M with features like:
- Up to 496 interrupt priority levels
- Shorter interrupt latency
- More flexibility in tail-chaining exceptions
- Deferred preemption for quicker ISR entry
The improved exception model allows Cortex-M processors to meet strict real-time requirements while running complex software stacks.
ARMv8-M also brings other enhancements like:
- Faster unprivileged execution
- Branch Target Identification (BTI) for control flow integrity
- Higher performance bus interfaces like AMBA 5 CHI
- Safer C programming model with bounds checking
ARMv8-M has seen rapid uptake since its release in 2015. Some of the Cortex-M cores leveraging the v8-M architecture include:
- Cortex-M23 – Microcontroller for embedded and IoT apps
- Cortex-M33 – MCU with DSP and FPU for advanced audio and ML workloads
- Cortex-M35P – First Cortex-M core with dual-core lockstep for functional safety
- Cortex-M55 – High-end industrial MCU with multicore DSP+FPU
- Cortex-M85 – New automotive MCU for zone control and computational storage
These new cores enable breakthrough capabilities in application areas like machine learning, digital signal processing, computer vision, and functional safety.
ARMv8-M represents a major evolution of the Cortex-M architecture. It expands the feature set with TrustZone, DSP instructions, enhanced security, and real-time capabilities. Leading-edge Cortex-M cores like Cortex-M33 and M55 now leverage ARMv8-M to meet the needs of innovative embedded and IoT designs across a diverse range of markets.