The ARM Cortex-R5 is a processor core designed by ARM Holdings for use in real-time embedded systems. It is part of the Cortex-R series of ARM processor cores, which are optimized for real-time performance and safety-critical applications.
Overview
The Cortex-R5 core is a 32-bit RISC processor optimized for high-performance real-time applications. It combines a dual-issue microarchitecture with extensive debug, trace, and error handling capabilities to enable the development of safety-critical systems that require certification to standards such as ISO 26262, IEC 61508, and DO-178B/C.
Some key features of the Cortex-R5 core include:
- Dual-issue pipeline capable of issuing and completing two instructions per cycle for high performance
- Dynamic branch prediction to improve performance of non-trivial conditional code
- Extensive error detection mechanisms like ECC on memories and buses
- Lock-step capability to enable dual modular redundancy (DMR)
- Memory protection unit (MPU) for software isolation
- Deterministic, low interrupt latency response
- Debug and trace support for observability and post-failure analysis
These capabilities allow the Cortex-R5 to deliver both high performance and functional safety capabilities required in markets like automotive, industrial, medical, aerospace etc. It is compatible with the ARMv7-R architecture profile and can execute Thumb-2 instruction set.
Architecture
The Cortex-R5 implements a 7-stage dual-issue superscalar pipeline combined with static branch prediction. The pipeline allows two instructions to be issued and completed in a single cycle, improving performance for appropriate code segments. The dual-issue pipeline has independent data paths for ALU and memory access operations.
The processor has a full ARMv7-R integer pipeline with support for 32-bit Thumb-2 instruction set. It can sustain single-cycle 32×32 bit integer multiply with 64-bit accumulate. The load/store architecture includes a 32-bit data cache and interfaces to 64-bit memory with ECC support.
For floating point, the Cortex-R5 relies on an optional floating point unit (FPU) implemented as a coprocessor. This allows flexibility in balancing die area and performance based on application requirements. The supported FPU can provide both single and double precision operations.
The branch prediction unit implements dynamic prediction with a 512 entry branch target cache. This improves performance for non-trivial conditional branches. For real-time applications, the dynamic prediction can be disabled to provide deterministic execution.
The processor includes lock-step logic to enable dual modular redundancy implementations. This provides a way to detect errors by running two instances of the core in parallel and comparing results. For memory protection, the Cortex-R5 implements a memory protection unit (MPU) with 8 regions and a background region. The MPU provides parameterization of memory attributes like cacheability, bufferability, shareability, access permissions etc.
Memory System
The Cortex-R5 core supports instruction and data caches to boost performance. The instruction cache is 8KB 4-way set associative with pseudo-round robin replacement. The data cache is 4KB 4-way set associative. Both caches use a write-through policy to ensure coherency with memory. The processor interfaces with 64-bit AHB, AXI or ACE interfaces to connect to memory and peripherals.
For functional safety support, the caches, TCM interfaces, and system buses implement error correction coding (ECC). This provides single error correction and double error detection on memories and interfaces. The ECC logic helps detect and recover from safety-critical memory errors.
The Cortex-R5 also includes tightly-coupled scratchpad memories – 16KB instruction tightly coupled memory (ITCM) and up to 64KB data tightly coupled memory (DTCM). The TCM provides low-latency, single-cycle access suitable for deterministic real-time applications.
Debug and Trace
For debug support, the Cortex-R5 implements ARM Embedded Trace Macrocell (ETM) for instruction and data tracing. This captures software execution in real-time for analysis and profiling. Trace data can be exported off-chip via trace ports. The processor also includes breakpoints, watchpoints, and Embedded Cross Trigger (ECT) for advanced debugging.
In addition, the core provides a Micro-Trace Buffer (MTB) which can capture critical program flow for post-failure analysis. The MTB acts as a circular buffer recording branches, exceptions, and context IDs to reconstruct events leading up to a failure.
For analyzing multicore failures, the processor provides the Cross Trigger Interface (CTI) for tracing interactions between cores. This enables debugging of complex safety-critical systems across multiple processors.
Real-Time Performance
The Cortex-R5 implements several microarchitectural features to enable real-time performance:
- Low interrupt latency – IRQs can be taken within 12 clock cycles
- Deterministic execution by disabling dynamic branch prediction
- Dual-issue pipeline with divide between ALU and memory ops
- Tightly-coupled memories for deterministic access
- Lock-step capability for fault detection in dual-core implementations
- ECC on memories and buses to detect and correct errors
These capabilities allow the Cortex-R5 to meet key real-time performance metrics like worst-case interrupt latency, best/worst-case execution times. Engineers can leverage these features to build systems that can reliably respond to external stimuli within strict time bounds.
Power Management
The Cortex-R5 implements extensive clock gating throughout the design to minimize power consumption. Software can control enabling of the instruction and data caches independently to deactivate units not required by a particular application. The processor also provides multiple power-down modes including a sleep mode that maintains processor state with low leakage.
In addition, the core supports multiple voltage domains to allow different voltage supplies for logic, memories, and I/Os. This provides further flexibility in optimizing power consumption for a target application.
Licensing and Manufacturing
ARM licenses the Cortex-R5 IP to semiconductor companies for integration into system-on-chip (SoC) designs. The processor is implemented as synthesizable RTL code, enabling licensees to target different foundry processes like TSMC, Samsung, GlobalFoundries etc. Leading vendors who have licensed the Cortex-R5 core include Texas Instruments, NXP, STMicroelectronics, Microchip, Renesas, among others.
These vendors offer the Cortex-R5 CPU in various configurations tailored for applications ranging from automotive engine control units to industrial motor drives to aerospace flight controllers. The R5 IP can be combined with application-specific logic, peripherals, memories, interconnect, and physical interface controllers on a SoC.
For example, Texas Instruments offers the Cortex-R5F based TMS570 automotive MCUs which combine the R5 CPU with checkers for safety, along with CAN, Ethernet, and ADC peripherals commonly used in automotive designs. NXP offers the S32K148 MCU for industrial applications integrating the Cortex-R5 with connectivity for protocols like EtherCAT used in factory automation.
Summary
The ARM Cortex-R5 is a high-performance real-time processor optimized for embedded control applications requiring functional safety and reliability. Key features include dual-issue pipeline, lock-step capability, MPU, low latency interrupts, advanced debug/trace, and ECC protection. The R5’s real-time capabilities enable it to meet critical timing requirements in domains like automotive, aerospace, medical, and industrial automation. With an optional FPU, it can handle applications needing floating point. The processor is licensed by ARM and available from vendors as synthesized IP or integrated on SoC products across a range of markets.
