The Arm Cortex-M0 is a 32-bit RISC processor core that implements the Arm Thumb instruction set architecture. It supports a highly optimized and efficient subset of the full Thumb instruction set that is designed specifically for microcontroller applications requiring minimal code size and low energy consumption.
Overview of Arm Cortex-M0
The Cortex-M0 processor is Arm’s smallest and most energy-efficient Cortex-M core. It is intended for use in microcontroller and deeply embedded applications that require strong real-time performance in an area-constrained system. Typical applications include sensors, wearables, home automation, small industrial equipment, and so on.
Key features of the Cortex-M0 core include:
- 32-bit RISC architecture with Thumb instruction set
- Up to 48MHz maximum clock frequency
- As little as 12KB code size with embedded Flash memory
- Single-cycle fast I/O interface
- Low energy – as little as 9uA/MHz
- Excellent real-time interrupt response
- Small silicon footprint
By leveraging an efficient RISC architecture and Thumb instruction set, the Cortex-M0 delivers outstanding performance per MHz, which allows it to operate at lower frequencies and voltages to minimize power consumption. The stripped down Thumb-2 instruction set is optimized for C compilers and achieves a reduced code size of 30-40% compared to legacy Arm cores.
Thumb and Thumb-2 Instruction Sets
To understand which instruction set the Cortex-M0 supports, it is useful to first understand Arm’s Thumb and Thumb-2 instruction sets.
Thumb is a 16-bit compressed instruction set that was originally designed to improve code density for Arm processors. By using 16-bit instructions instead of 32-bit instructions, Thumb can reduce code size by around 30% while retaining most of the performance. The first version of Thumb was introduced in Armv4T architectures.
Thumb-2, first introduced in Arm11 cores, is an extension of the Thumb instruction set that provides both 16-bit and 32-bit instructions. The 16-bit Thumb instructions are for high-density code while the 32-bit instructions provide additional functionality and performance. Thumb-2 provides full compatibility with the Arm instruction set while retaining the code size benefits of Thumb.
All modern Arm Cortex processor cores, including the Cortex-M0, support the Thumb-2 instruction set. However, the Cortex-M0 implements a subset of Thumb-2 designed specifically for embedded and microcontroller applications.
Cortex-M0 Thumb Instruction Set
The Cortex-M0 core supports a highly optimized Thumb instruction set called Thumb-2 Technology for Embedded (Thumb-2 TE). This implements a subset of the full Thumb-2 instruction set that includes only the instructions commonly used in embedded applications.
Key features of the Thumb-2 TE instruction set used by Cortex-M0:
- 16-bit and 32-bit instructions for optimal code density
- Up to 40% better code density than early Arm cores
- Subset of full Thumb-2 ideal for embedded apps
- Includes dual-issue 16-bit Thumb instructions
- No support for SIMD, floating point, or divide instructions
- Tailored for C compilers with interworking
- Low power features like event-driven wake up
By eliminating less commonly used instructions like floating point and SIMD, the Thumb-2 TE instruction set provides all the functionality needed for deeply embedded microcontroller applications while minimizing size, complexity, and power consumption.
The dual-issue 16-bit Thumb instructions allow two 16-bit instructions to be executed in parallel in a single cycle, boosting performance. Interworking support allows switching between Arm and Thumb states efficiently.
Overall, the streamlined Thumb-2 TE instruction set enables Cortex-M0 cores to achieve exceptional code density, performance, and power efficiency when running embedded software.
Supported Data Types
Since the Cortex-M0 is a 32-bit RISC core, it supports 32-bit arithmetic operations on the following data types:
- 32-bit integers
- 16-bit shorts
- Characters and booleans (8-bit)
- 32-bit pointers
- 32-bit and 64-bit floating point (in software)
Being a RISC architecture, data types such as characters and booleans still use full 32-bit registers. The small 8kB register file is optimized for fast context switching.
The processor operates on 8-bit, 16-bit, and 32-bit data without any performance penalty – all data types use the 32-bit ALU. Memory access can be 8-bit, 16-bit, or 32-bit. The barrel shifter supports shift and rotate operations on 32-bit values.
Notable Instruction Groups
Here are some examples of the types of instructions supported in the Thumb-2 TE subset used by Cortex-M0:
- Data Processing – Arithmetic, logical, and move instructions on 32-bit registers
- Load/Store – Load or store 8/16/32-bit data between registers and memory
- Branch – Branch instructions for changes in program flow
- Supervisor Call – Instructions for entering privileged/kernel modes
- Coprocessor – For interfacing with optional FPU or DSP
- PUSH/POP – Push or pop stack operations on internal stack
- Hint – Instructions giving hints to the processor
These allow the Cortex-M0 to perform all the basic operations needed for an embedded microcontroller – arithmetic logic, controlling program flow, accessing memory, controlling peripherals, managing stacks, and more.
Unsupported Instructions
As mentioned earlier, the Thumb-2 TE instruction set specifically excludes certain instruction groups to minimize size and complexity for embedded applications:
- No floating point instructions
- No SIMD or media instructions
- No hardware divide instructions
- No virtualization support
- No cache maintenance or prefetch instructions
Any floating point math must be handled via software libraries. Code density is favored over raw performance in the deeply embedded space where Cortex-M0 is targeted.
Instruction Set Architecture Summary
In summary:
- The Arm Cortex-M0 implements the Thumb-2 Technology for Embedded (Thumb-2 TE) instruction set.
- This is a optimized 16/32-bit Thumb-2 subset for embedded microcontrollers.
- It provides all commonly used instructions to minimize code size.
- Excludes less frequently used instructions like floating point and divide.
- Ideal instruction set architecture for low-cost, low-power embedded applications.
By leveraging Thumb-2 TE, the Cortex-M0 achieves outstanding performance, power efficiency, and code density making it well-suited for modern embedded and IoT applications requiring a 32-bit RISC microcontroller.
