The ARM Cortex series of processors utilize a number of special purpose registers that allow for customized control and monitoring of the processor’s operation. These registers give developers and engineers visibility into the internal workings of the processor and enable optimization of performance, power usage, and functionality.
The program counter (PC) register contains the memory address of the next instruction to be executed. It is automatically incremented during sequential instruction execution. The PC can be manipulated to implement branches and jumps by loading a new value into it. Upon exception entry, the PC is saved to the link register so that execution can resume afterwards.
The link register (LR) stores the return address when a branch is taken or an exception occurs. This allows execution to continue from the original location after the branch or exception handler completes. The LR register can also be used as a general purpose register if not needed for return addresses.
The stack pointer (SP) register indicates the top of the stack in memory. It is used to push and pop data to/from the stack. Stack operations like pushes and pops automatically update the SP. Manipulating this register allows control over the stack position. Upon exception entry, the SP and LR are saved to the stack.
The condition flags (NZCV) record the results of arithmetic operations, such as carries, overflows, zeros, and negatives. These flags can be tested with conditional execution instructions to implement branches and loops based on certain arithmetic outcomes. Common conditional flags include:
- N – Negative flag
- Z – Zero flag
- C – Carry flag
- V – Overflow flag
The control register governs key elements of control and data processing operations. Typical bits include:
- M – Mode field for selecting processor mode
- I – Interrupt disable bit
- F – FIQ disable bit
- T – Thumb execution state bit
Modification of the control register can be used to switch between ARM and Thumb instruction sets, change processor modes, and enable/disable interrupts.
The status register provides information about the processor state. It exposes the following:
- Processor mode
- Interrupt disable status
- Overflow status
- Carry/borrow status
The status register gives visibility into key details about the current processor context. This can be useful for debugging, profiling and dynamic control of applications.
Exception Link Register
The exception link register (ELR) holds the address to return to after handling an exception. When a synchronous exception occurs, the ELR receives the address of the instruction that triggered it. For asynchronous exceptions, it gets the address of the instruction boundary.
Saved Program Status Register
The saved program status register (SPSR) stores a copy of the CPSR register on exception entry. This saves the CPSR context so it can be restored when the exception handler completes. The SPSR is used alongside the ELR to return properly to the original execution context.
A set of instruction registers hold instructions fetched from memory prior to execution. Typical instruction registers include:
- Current Program Status Register – Holds the instruction being executed currently
- Next Executing Instruction – Fetched instruction to execute after the current one
- Fetched Instruction Queue – FIFO queue holding pending instructions
These registers enable efficient pipelined execution by prefetching instructions before they are required. This hides some of the instruction fetch latency.
The decoder register holds instruction decoding information, such as:
- Instruction length
- Location of operands
- Execution mode (ARM vs Thumb)
By buffering this information in a register, the decoding logic can be simplified to improve performance and reduce power usage.
Memory Protection Unit Registers
The memory protection unit (MPU) utilizes registers for configuring memory access permissions. These include:
- Number of programmable MPU regions
- Start and end address for each region
- Access permission control fields
- MPU control bits
The MPU registers allow dynamic control over memory access permissions for security and safety purposes in critical systems.
Floating Point Registers
Dedicated floating point registers augment the general purpose registers to provide efficient storage for floating point operands and results. These can include:
- Floating point status and control register
- Floating point exception register
- A set of floating point data registers
Segregating floating point and integer registers maximizes opportunities for parallel execution of floating point intensive code.
Advanced SIMD/NEON Registers
To enable high performance vector operations, ARM Cortex processors often include a set of SIMD (Single Instruction Multiple Data) registers, marketed under the NEON brand. NEON provides features such as:
- 32 x 128-bit data registers
- Dedicated saturating arithmetic instructions
- Advanced rounding modes
- Extensive data reordering operations
NEON enables significant acceleration of media processing, imaging, computer vision and digital signal processing algorithms.
For debugging complex embedded systems, ARM processors contain specialized debug registers and logic. These provide capabilities including:
- Halting debug events
- Invasive and non-invasive debug
- Trace buffers
Debug registers give visibility into the processor state during critical points of program execution.
Thumb Execution Environment Register
The Thumb execution environment register indicates whether the processor is currently in ARM or Thumb execution state. This allows the execution mode to be switched automatically when calling or returning from Thumb/ARM routines.
Nested Vectored Interrupt Controller Registers
The nested vectored interrupt controller (NVIC) registers provide low-latency exception Prioritization and control. Key attributes include:
- Set/clear pending interrupts
- Set interrupt priority levels
- Determine active interrupt number
- Trigger software interrupts
These registers deliver real-time responsiveness for interrupt-driven embedded systems.
System Control Block Registers
The system control block provides overall configuration capability for the rest of the processor. Useful SCB registers include:
- Vector table offset register
- Application interrupt and reset control register
- System timer registers
- Processor feature control bits
SCB registers allow customization of reset behavior, timer services, exceptions, and general configuration options.
In summary, ARM Cortex processors contain a rich assortment of special registers to control and monitor all aspects of processor operation. Developers can leverage these registers to build optimized and robust embedded systems. The program counter, link register, stack pointer, and condition flags provide basic yet crucial execution monitoring. Control, status, and exception handling registers assist with complex application code. Memory protection, floating point, SIMD and debug registers enable further acceleration and safety capabilities. Overall the extensive special registers make the ARM Cortex family exceptionally flexible and powerful.