The Arm Cortex-M4 processor has multiple operating modes to provide different levels of access and control over system resources. The main operating modes are Thread mode, Handler mode, and Privileged mode. Additionally, the Cortex-M4 implements the Fault exceptions model which allows fast exception handling for common fault conditions.
Thread Mode
Thread mode is the primary operating mode where most application code executes. In Thread mode, the processor has limited access to system resources and peripherals. Thread mode provides unprivileged access and is mainly used to execute non-privileged background tasks and applications.
The key features of Thread mode are:
- Used to execute non-privileged background tasks and applications
- Provides unprivileged access to system resources
- Cannot access system control registers directly
- Can only execute unprivileged instructions
- Uses MSP (main stack pointer) for function calls and returns
When executing in Thread mode, the processor cannot access protected system resources directly. Any attempt to execute a privileged instruction will trigger a fault exception and switch to Handler mode.
Handler Mode
Handler mode is used to handle exceptions and interrupts. When an exception occurs, like an access violation or divide by zero, the processor switches from Thread mode to Handler mode to quickly handle the exception.
The key features of Handler mode are:
- Used to handle exceptions and interrupts
- Automatically entered on exceptions
- Can access full Cortex-M4 resources
- Uses MSP (main stack pointer) for function calls
- Returns to original context on completion
In Handler mode, the processor has full access to the Cortex-M4 resources to handle the exception condition. This includes system control registers and privileged instructions. Once the exception is handled, the processor returns to the original context in Thread mode.
Privileged Mode
Privileged mode provides full unrestricted access to all Cortex-M4 resources. This mode is reserved for privileged system level code like the OS kernel.
The key features of Privileged mode are:
- Provides full unrestricted access to all resources
- Used for privileged system level code
- Accessed using privileged instructions
- Uses PSP (process stack pointer) for function calls
- Often requires context switch on entry/exit
Since Privileged mode provides complete access, switching to this mode usually requires a context switch to change stack pointers and registers. This mode allows privileged code to access protected system resources for implementing OS functionality.
Fault Exceptions Model
The Cortex-M4 implements the Fault exceptions model to provide fast exception handling for common fault conditions. This allows frequently occurring exceptions like access violations to be handled efficiently.
The key fault exceptions are:
- HardFault – For undefined instructions and more serious faults
- MemManage – On MPU memory access violations
- BusFault – On bus errors during memory or peripheral access
- UsageFault – On illegal use of instructions
- DebugMonitor – When debug is enabled, allows debugger to gain control
These fault exceptions have priority over normal interrupts. When a fault occurs, the processor immediately enters Handler mode, pushes registers to the stack, and executes the fault exception handler. This simplifies and speeds up handling common fault conditions.
Context Switching
Switching between different operating modes requires context switching to change stack pointers and save processor state information. This is done using special exception entry and return mechanisms.
On an exception entry:
- Processor pushes registers to stack
- Changes to Handler mode and MSP stack
- Jumps to exception handler
On exception return:
- Stack and registers restored
- Returns to previous Thread mode context
These mechanisms allow fast switching between Thread mode and Handler mode on exceptions. Switching to Privileged mode requires more complex context switching to change stack pointers and save additional state.
Inter-mode Communication
The Cortex-M4 provides mechanisms for communication between different modes using SVCall and PendSV exceptions.
- SVCall – Allows switching from Thread to Handler mode on SW request
- PendSV – Triggers context switch from Handler to Thread mode
This allows Thread mode code to make OS service calls using SVCall, which results in a context switch to Handler mode. The OS can then perform inter-thread communication and use PendSV to return to Thread mode.
Privileged Access Control
The Memory Protection Unit (MPU) and Protected Register Access (PRAc) controls provide configurable privileged access control to resources.
Key features include:
- MPU – To control access permissions for up to 16 memory regions
- PRAc – To configure privileged access to peripherals and registers
- Different privilege levels for unprivileged Thread mode and privileged Handler/Privileged modes
This allows system designers to implement schemes for protecting and partitioning resources between different execution contexts based on privilege levels.
Summary
The Cortex-M4 operating modes provide a layered privilege architecture to securely separate application and system level code. Thread mode executes non-privileged code with limited access. Handler mode enables fast exception handling. Privileged mode runs fully trusted system code. The MPU and PRAC add further access control capabilities.
Overall, these features allow system designers to implement complex mixed-criticality applications with both security and real-time performance.
