The ARM architecture defines a set of exceptions that can occur during program execution. These exceptions, also known as interrupts, allow the processor to handle events and transfer control to specific software routines to deal with these events. Some key things to know about exceptions in ARM architecture:
Types of Exceptions
There are several different types of exceptions defined in the ARM architecture:
- Reset – This exception occurs when the processor is reset. It causes the program counter to jump to the reset vector address.
- Undefined instruction – Triggered when an undefined or unimplemented instruction is executed.
- Software interrupt – This is a program-triggered exception by executing the SWI instruction.
- Prefetch abort – An instruction prefetch resulted in an abort, such as an invalid memory access.
- Data abort – An data memory access operation resulted in an abort, such as invalid memory access.
- IRQ – Standard interrupt request triggered by an external device or event.
- FIQ – Fast interrupt request which has higher priority than IRQ.
Exception Vectors
Each exception type has a corresponding vector – an address pointing to the exception handler routine. The processor jumps to this address when the exception is triggered.
The exception vector addresses are defined by the ARM architecture. For example, the reset vector is 0x00000000, the undefined instruction vector is 0x00000004, and so on.
Developers can implement custom exception handler routines at these vector addresses to respond to exceptions in the desired way.
Processor States on Exception Entry
When an exception occurs, the ARM processor automatically saves its state before jumping to the vector. This includes:
- Saving the program counter (PC) to the link register (LR)
- Switching to a new mode – e.g. from User mode to Supervisor mode
- Saving the SPSR (Saved Program Status Register)
This preserves the state so that the main program can resume after the exception handler runs.
Return From Exception
Once the exception handler completes its work, it returns control back to the main program using the subs instruction. This restores the PC, CPSR and other registers from the stored values.
The exception return offsets are predefined for each exception type. This allows the handler to return to the instruction after the point where the exception occurred.
Enabling and Disabling Interrupts
The ARM processors provide mechanisms to enable and disable interrupts such as IRQ and FIQ. This is useful for critical sections of code where interrupts must be temporarily blocked.
Common ways to enable/disable interrupts include:
- Setting or clearing the I and F bits in the CPSR using MRS/MSR instructions
- Using CPS instructions to modify the interrupt disable flags
- Storing and restoring CPSR during exception entry/exit
Disabling interrupts for long periods can impact real-time performance, so care must be taken.
Nested Exceptions
It is possible for an exception to occur while another exception handler is already running. This is called nested exceptions.
ARM processors include mechanisms to handle nested exceptions safely by stacking additional context during nested exception entry.
However, nested exceptions can make interrupt handling complex for developers. They should generally be avoided in application code if possible.
Prioritizing Exceptions
In ARM architecture, exceptions have a defined priority order. Higher priority exceptions can interrupt lower priority ones.
The exception priorities are, from highest to lowest:
- Reset
- Data abort
- FIQ
- IRQ
- Prefetch abort
- Undefined instruction
- Software interrupt
So for example, an FIQ interrupt will preempt a currently executing IRQ handler. But a lower priority Software Interrupt cannot preempt an FIQ.
Secure and Non-secure Exceptions
ARMv8 architectures introduce TrustZone and security extensions. This allows certain exceptions to be designated as “secure” while others are “non-secure”.
Secure exception handlers run with higher privileges and can access secure resources. Non-secure exceptions have limited access.
This exception model separation improves security in IT systems.
Summary
In summary, exceptions allow ARM processors to respond efficiently to events during program execution. The ARM architecture precisely defines various exceptions, their priorities, vector addresses, return mechanisms, and security models. Developers can leverage exceptions to build robust interrupt handling in their ARM-based systems.
