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Arm

Vitis limitations on Cortex-M1 architectures and workarounds

Eileen David
Last updated: September 17, 2023 12:07 pm
Eileen David 6 Min Read
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The Xilinx Vitis unified software platform provides a development environment for creating embedded software applications targeting Arm Cortex-M class processors, including the Cortex-M1. However, there are some limitations when using Vitis to build applications for Cortex-M1-based systems.

Contents
Limited BSP and driver supportNo automatic compiler optimizationsLimited memory footprint tuningMinimal low-power design automationLack of CMSIS integrationMinimal real-time analysisLimited RTOS integrationNo Cortex-M1 specific project templatesLack of TrustZone supportSummary

Limited BSP and driver support

The Vitis ecosystem currently has limited board support package (BSP) and driver support for Cortex-M1 devices compared to more widely used Cortex-M3/M4 chips. The BSP provides the low-level libraries and drivers needed to boot and run an application on a particular hardware platform. Many common peripherals like Ethernet, USB, and display controllers have Cortex-M3/M4 drivers available but lack Cortex-M1 support in Vitis.

Workaround: Check the device datasheet and write custom drivers for any unsupported peripherals required by your application. Refer to the Vitis driver development guide on adding new BSP drivers. Reusing code from open-source Cortex-M1 driver projects can help accelerate the process.

No automatic compiler optimizations

The Vitis compiler does not automatically generate highly optimized code for the Cortex-M1 like it does for Cortex-M3/M4. Certain processor-specific optimizations like thumb instruction selection, unconditional execution optimization, and single-cycle I/O port access are not enabled by default with -O2 optimization level for Cortex-M1.

Workaround: The compiler flags -mthumb, -mno-unaligned-access, and -msingle-pic-base will enable some of these optimizations manually. Profile guided optimization can help further improve performance if runtime metrics are available. You may also customize the linker script to take advantage of Cortex-M1 architectural features.

Limited memory footprint tuning

Memory utilization is critical for Cortex-M1 microcontrollers, but Vitis offers fewer options to analyze and reduce application memory footprint compared to advanced tools like Keil MDK with its linker map viewer. The Vitis IDE provides basic reports on stack usage but lacks a detailed visualized linkage map.

Workaround: Use compiler options like -ffunction-sections -fdata-sections to generate function-level granularity for code, then customize the linker script to remove unused sections. The open-source arm-none-eabi toolchain with the Lauterbach Trace32 debugger can also help provide better visibility into memory usage.

Minimal low-power design automation

Reducing power consumption is vital in many Cortex-M1 applications. However, Vitis does not automate the process of clock gating unused peripherals, generating wait states, or leveraging low-power modes. This requires manual coding of power management techniques.

Workaround: Use general strategies like minimizing unnecessary memory accesses, using lower clock frequencies, disabling peripherals when not active, and putting the processor in sleep mode when idle. Tools like Arm Keil ULP Advisor can also help guide power optimization of Vitis applications.

Lack of CMSIS integration

The Cortex Microcontroller Software Interface Standard (CMSIS) provides a vendor-independent hardware abstraction layer for Arm Cortex-M processors. However, Vitis does not fully integrate CMSIS support and its device header files for Cortex-M1 targets.

Workaround: The CMSIS headers for your specific Cortex-M1 device need to be manually included in your Vitis project to leverage its utilities for managing the processor core, peripherals, and interrupts. CMSIS functions like SysTick or NVIC access may need custom adaptation code.

Minimal real-time analysis

Vitis lacks detailed real-time performance analysis and debugging capabilities that are important for deterministic, time-sensitive Cortex-M1 applications. There are no task timing measurements or system load metrics available within Vitis IDE.

Workaround: Use an external logic analyzer or profiler to validate real-time deadlines and execution latencies. Trace-based debugging tools like SEGGER SystemView or Lauterbach TRACE32 provide greater real-time visibility compared to Vitis debugger.

Limited RTOS integration

Many Cortex-M1 designs use a real-time operating system (RTOS), but Vitis has minimal built-in integration with popular RTOS like FreeRTOS. RTOS-specific project configuration, thread profiling, visualization, and debugging features are not available.

Workaround: RTOS porting and configuration needs to be done manually based on vendor guides. Alternate IDEs like MCUXpresso provide better RTOS support and should be considered if a priority. Use RTOS-aware debuggers like SEGGER Ozone to improve multithreading visibility.

No Cortex-M1 specific project templates

Vitis lacks dedicated project templates optimized for Cortex-M1 development. Users need to manually configure Cortex-M1 specific settings like Thumb code generation and linker scripts for each new project.

Workaround: Create custom Vitis Cortex-M1 application projects or makefiles that encapsulate the required configurations, BSPs, and linker scripts. These can serve as the starting point for new projects. Some vendor development boards have predefined Cortex-M1 templates.

Lack of TrustZone support

The Cortex-M1 supports Arm TrustZone security extensions, but Vitis currently cannot generate code to leverage TrustZone secure and non-secure worlds. This prevents utilizing hardware isolation mechanisms for trusted execution and cryptography acceleration.

Workaround: Implement a software infrastructure to emulate limited privilege separation across code sections, and use external secure elements for cryptographic operations. Upcoming Vitis releases are expected to add initial support for TrustZone on Cortex-M class processors.

Summary

In summary, key limitations when using the Xilinx Vitis tools for Cortex-M1 processor-based designs include lack of optimized drivers, compilers, memory reduction capabilities, power management support, real-time analysis, and RTOS integration compared to Cortex-M3/M4 support. Developers can workaround these deficiencies through manual optimization techniques, external tools, and creating custom design templates optimized for Cortex-M1. As Vitis matures, Cortex-M1 support will likely improve in future releases.

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