The Pynq-Z1 board features both a dual-core ARM Cortex-A9 processor system (PS) and a Cortex-M1 real-time processor. The AXI interconnect allows communication between these heterogenous processors, enabling users to leverage the benefits of both in their designs.
Overview of Pynq-Z1 Architecture
The Pynq-Z1 is built around a Xilinx Zynq XC7Z020 SoC. This SoC contains both the PS and PL (programmable logic) sections. The PS includes the dual-core ARM Cortex-A9 processor while the PL is based on Xilinx 7-series FPGA fabric. In addition to the Zynq SoC, the Pynq-Z1 board contains external DDR memory, onboard peripherals like Ethernet, USB, HDMI, etc. and the Microblaze soft-core processor.
A key component of the Pynq-Z1 architecture is the Cortex-M1 subsystem. This is a 32-bit RISC processor optimized for real-time applications. It is implemented in the PL and communicates with the PS using AXI interconnects. The Cortex-M1 along with its peripherals and interrupts forms the real-time domain while the PS forms the non-real-time domain.
Benefits of Cortex-M1 and AXI Interconnect
The presence of the Cortex-M1 microcontroller domain on the Pynq-Z1 provides several benefits:
- Real-time processing: The Cortex-M1 has deterministic timing making it ideal for tasks requiring low latency and real-time control.
- Offloading PS: Compute intensive real-time tasks can be offloaded from the PS to the Cortex-M1. This reduces load on the PS.
- Custom hardware integration: The Cortex-M1 has tight integration with the PL enabling users to easily incorporate custom hardware accelerators.
- RTOS support: The Cortex-M1 supports real-time operating systems like FreeRTOS allowing greater software flexibility.
However, to take advantage of these benefits the Cortex-M1 must efficiently communicate with the PS. This is achieved using AXI interconnects between the PS and PL.
AXI Interconnect Overview
The Advanced eXtensible Interface (AXI) is a parallel high-speed interconnect protocol developed by ARM. It enables communication between components like processors, peripherals and memory controllers.
Some key features of AXI are:
- Separate address, data and control channels
- Burst based transactions for high efficiency
- Supports multiple outstanding transactions
- Options for arbitration, width translation and clock crossing
The Zynq SoC implements multiple AXI interconnects between the PS and PL. This includes both high-performance interconnects (HP) and general purpose interconnects (GP). There are also AXI ports to DDR and OCM memories.
Connecting Cortex-M1 and PS using AXI
On the Pynq-Z1, the Cortex-M1 interfaces with the PL using AXI ports. To connect it with the PS, these ports must be wired to the HP or GP AXI interconnects. This enables seamless communication between the PS and Cortex-M1 using standard AXI transactions.
Some ways the AXI interconnect can be utilized are:
- Cortex-M1 reading/writing PS DDR memory for data sharing
- PS accessing peripherals attached to Cortex-M1
- Cortex-M1 interrupting PS to notify events
- PS controlling or monitoring Cortex-M1 execution
The AXI interconnect enables all this while abstracting away the implementation details. Software running on the PS and Cortex-M1 only needs to perform regular load/store instructions to access interconnects mapped into their memory space.
Design Considerations
When utilizing the AXI interconnects between the PS and Cortex-M1, developers must consider:
- Interconnect bandwidth – The HP interconnects provide higher throughput than GP. Bandwidth requirements must be analyzed.
- Data coherency – AXI does not implement cache coherency. Software must flush caches if shared data is modified.
- Transaction ordering – Interconnects might reorder transactions. Ordering requirements must be met in software.
- Arbitration – Contention may occur if multiple masters access interconnect. Arbitration schemes should be configured.
Software Architecture
To leverage both the PS and Cortex-M1 effectively, a robust software architecture is required. Some recommendations are:
- Bare-metal or FreeRTOS on Cortex-M1 for real-time tasks
- Linux/Bare-metal on PS for complex application processing
- Well defined APIs for inter-processor communication
- Modular application partitioning between processors
- Interrupt handlers and mailbox mechanisms for event notifications
With appropriate software design, the dual processor architecture of the Pynq-Z1 can be used efficiently.
Example Designs
Some example projects using both the PS and Cortex-M1 are:
- Real-time motor control – Cortex-M1 performs closed loop control while PS provides user interface.
- Sensor hub – Cortex-M1 manages sensor data acquisition while PS processes and analyzes data.
- Neural network inference – Cortex-M1 serves as command processor while PS runs inference engine.
These showcase the unique capabilities enabled by the tight coupling between the PS and Cortex-M1 processors via the AXI interconnect.
Conclusion
The AXI interconnect provides an efficient means of communication between the PS and Cortex-M1 on the Pynq-Z1 board. This enables users to leverage the benefits of both processors in their designs – real-time performance of Cortex-M1 along with software programmability of PS. With appropriate considerations for bandwidth, coherency, arbitration and software architecture, the capabilities of both processors can be fully utilized leading to optimized design implementations.
