The register file is a key component of the ARM Cortex-M0 and Cortex-M3 microcontroller cores. It contains the general purpose registers that are used to store data during program execution. Understanding the diagram and layout of the register file provides useful insights into the architecture and operation of these microcontroller cores.
Overview of Cortex-M0/M3 Register File
The Cortex-M0/M3 register file contains 16 32-bit general purpose registers, labeled R0-R15. These registers can be used to store data like variables, addresses, results of computations, etc. The register file allows very fast access to these registers, allowing the CPU to fetch or store register contents in a single cycle.
In addition to the 16 general purpose registers, there are two more 32-bit registers that are part of the register file – the program counter (PC) and the program status register (PSR). The program counter contains the address of the next instruction to fetch, while the program status register contains status flags like the interrupt mask, overflow flag, carry flag, etc.
The register file is closely integrated with the execution pipeline of the Cortex-M0/M3 cores. It provides two read ports and one write port to allow simultaneous fetching of operands and writing back of results. All registers can be accessed in a single cycle.
Detailed Register File Diagram
The detailed diagram of the Cortex-M0/M3 register file is shown below:
The key components of the register file are:
- 16 general purpose 32-bit registers R0-R15
- 32-bit program counter PC
- 32-bit program status register PSR
- 2 read ports (Read data 1, Read data 2)
- 1 write port (Write data)
- Write register select
- Read register 1 select
- Read register 2 select
General Purpose Registers
The general purpose registers R0-R15 are 32-bit wide registers used to store operand data as well as results of computations. They can be accessed very efficiently in a single cycle. R0-R12 are general purpose registers used to store temporaries, variables, etc. R13 is used as the stack pointer. R14 is used as the link register to store return addresses when calling subroutines. R15 or PC is the program counter.
This 32-bit register holds the address of the next instruction that needs to be fetched from memory. It increments by 4 bytes after every instruction fetch. Conditional branches or exception returns can modify the PC to redirect execution.
Program Status Register
The 32-bit PSR holds several status flags that control the operation of the processor. This includes the APSR, EPSR and IPSR registers. Key flags include the negative, zero, carry, and overflow flags used for arithmetic status. Interrupt masking and triggering flags are used for exception handling.
The register file provides two read ports and one write port to support simultaneous read and write operations in a cycle. The write port allows writing the result of an ALU operation to a destination register. The two read ports allow simultaneous fetching of two source operands to the ALU.
Read/Write Control Signals
The read and write operations to the register file are controlled using the following signals:
- Write register select – Specifies which register to write to
- Read register 1 select – Specifies first operand source register
- Read register 2 select – Specifies second operand source register
Accessing the Register File
The register file can be accessed in different ways by the instructions in the Cortex-M0/M3 architecture:
Load instructions like LDR fetch data from memory and store it in a register. Store instructions like STR store data from a register to memory. One of the read ports is used to read the address register, while the other read port allows simultaneous fetch of the data register for stores.
Arithmetic/logic instructions like ADD, XOR, etc operate on source registers to produce a result that is written back to a destination register. The two read ports fetch the two source operands, while the result is written back using the write port.
Jumps and Branches
Instructions like B, BL, etc can modify the PC in case of branches or function calls. This causes the register file to feed a new instruction address for the next fetch cycle.
Exceptions like interrupts or faults cause context saving of registers to the stack using store instructions. The return from exception may restore register context using load instructions.
Benefits of the Register File
Some benefits of the Cortex-M0/M3 register file design are:
- Very low latency access enables single cycle operand fetch/writeback
- Having 16 general purpose registers allows flexible register usage in code
- Dedicated PC and PSR registers simplifies implementation of key functions like branches, interrupts, etc
- Two read ports allows simultaneous fetch of operands
- Single write port enables writeback of ALU results
- Compact implementation consumes less power and silicon area
Some examples of how the register file is used during program execution are:
Data Processing Operations
When adding two numbers stored in R1 and R2 and placing result in R3:
Cycle 1: R1 and R2 read via two read ports
Cycle 2: ADD result written back to R3 via write port
When loading a value from an address in R1 to R2:
Cycle 1: R1 (address register) read via read port 1
Cycle 2: Load data from memory to R2 via write port
When BLX instruction calls a subroutine:
Cycle 1: R14 (link register) and PC (return address) written to stack
Cycle 2: PC updated to branch target address
The register file is a critical component that enables fast access to registers in Cortex-M0/M3 cores. The diagram shows the major elements like general purpose registers, dedicated PC and PSR registers, read/write ports and control signals. Understanding how instructions access the register file provides insights into the microarchitecture. The dual read ports and single write port facilitates parallel fetch and writeback. Overall, the register file allows efficient register usage for program temporary data, addresses, branch handling and exception processing.
In this article, we looked at the internal diagram and organization of the register file in Cortex-M0 and Cortex-M3 microcontrollers. The register file provides low latency access to 16 general purpose registers and special registers like PC and PSR through dual read ports and a single write port. Instructions can simultaneously access multiple registers to efficiently execute ADD, LOAD, STR type operations in a single cycle. The register file is an integral part of the CPU architecture enabling quick context switching, branch handling and exception processing. Understanding the register file gives insights into the microarchitecture design and performance of Cortex-M cores.