The ARM Cortex-M3 processor provides extensive support for system power management. This allows the Cortex-M3 system to operate in different power modes depending on the required operation and enabling energy saving. The Cortex-M3 processor provides flexible power management schemes to optimize the power/performance requirements of end applications.
Cortex-M3 Power Modes
The Cortex-M3 processor supports several power modes for managing system power consumption. The main power modes are:
- Active Mode: The processor operates normally, executing code as required.
- Sleep Mode: The processor clock is disabled, but retains the contents of registers and SRAM. Wake up latency is fast.
- Deep Sleep Mode: All clocks are disabled. SRAM retention is optional. Wake up latency is slow.
- Standby Mode: Only backup domain is powered on to maintain RTC and wakeup logic. Fastest wake up latency.
In Active mode, the system clocks are enabled and the processor fetches and executes instructions as needed. This provides the highest performance, but also consumes the most power.
In Sleep mode, the core clocks are disabled, so the processor stops executing instructions. However, SRAM contents and register contents are maintained. Sleep mode saves power consumption while providing fast wake-up latency.
In Deep Sleep mode, all clocks including peripherals and SRAM are disabled. This provides low power consumption, but has higher wake-up latency than Sleep mode. SRAM retention can be enabled optionally in Deep Sleep mode.
In Standby mode, only the low power backup domain remains powered on. This domain maintains the RTC and wakeup logic. Standby mode has the lowest power consumption but takes longer to wake up than Deep Sleep mode.
Power Control Signals
The Cortex-M3 employs several power control signals to manage power modes:
- SLEEPDEEP: Set to 1 for Deep Sleep, 0 for Sleep Mode
- SLEEPHOLDREQn: Can delay sleep entry
- WICENACK: Wakeup interrupt controller acknowledge
- EVENTI: Event input for wakeup
- SLEEPEXIT: Sleep exit signal
The SLEEPDEEP signal determines whether the processor enters Sleep or Deep Sleep mode when the WFI or WFE instruction is executed. When SLEEPDEEP=0, Sleep mode is entered. When SLEEPDEEP=1, Deep Sleep mode is entered.
The SLEEPHOLDREQn signal can override sleep mode entry. Assertion of SLEEPHOLDREQn delays entry to a sleep mode.
The WICENACK signal is an acknowledge signal back to the interrupt controller that the wakeup interrupt has been received and is being processed.
The EVENTI input allows external events to trigger wakeup from Deep Sleep mode.
The SLEEPEXIT signal indicates when the processor is exiting a sleep mode.
Power Management Unit
The Cortex-M3 processor contains a Power Management Unit (PMU) that controls processor power modes and clock gating. The functions of the PMU include:
- Controls entry to processor power modes
- Controls clock gating and enables clocks
- Controls SRAM retention and power down
- Generates wakeup interrupts as needed
The PMU receives the SLEEPDEEP, SLEEPHOLDREQn, and WICENACK signals to control power mode entry and wakeup. It also receives the EVENTI input to trigger wakeup.
The PMU controls enabling and disabling of clocks to different processor modules using clock gating. Individual peripheral clocks can be gated off in Deep Sleep mode to save additional power.
In Deep Sleep mode, the PMU can optionally keep SRAM powered on to retain contents. This is enabled through the Memory Retention Control Register in the System Control Space.
The PMU will also automatically generate wakeup interrupts as needed, for example on an EVENTI trigger while in Deep Sleep mode.
Wakeup Interrupts
Wakeup interrupts play a key role in managing power modes of the Cortex-M3 system. When the processor enters Sleep or Deep Sleep mode, it will wake up on assertion of a wakeup interrupt. Wakeup interrupts have the highest priority to ensure fast response.
Some examples of wakeup interrupt sources are:
- External interrupt signal
- RTC alarm or tick interrupt
- GPIO pin change
- Peripheral interrupts
An external interrupt signal can be tied to the NVIC’s NMI (Non Maskable Interrupt) input to trigger a high priority wakeup from any low power mode. Alternatively, normal IRQ interrupts can also wakeup the processor.
The RTC (Real Time Clock) present in the Cortex-M3 system can generate scheduled tick or alarm interrupts to wakeup the system periodically from a low power state.
GPIO pin changes can also trigger interrupts and wakeup if enabled through the NVIC and GPIO interrupt logic.
Peripheral modules such as UART, I2C, SPI etc can raise interrupts when they need processor interaction due to external stimulus. These peripheral interrupts will wake the system from low power mode.
Power Mode Transitions
The Cortex-M3 processor performs power mode transitions on executing specific instructions or on interrupt/event triggers. The main transitions are:
- Active to Sleep: On executing WFI instruction
- Active to Deep Sleep: On WFI instruction when SLEEPDEEP=1
- Sleep/Deep Sleep to Active: On wakeup interrupt
- Active to Standby: On executing WFE instruction
- Standby to Active: Reset or external wakeup event
The WFI (Wait For Interrupt) instruction allows transition from Active mode to Sleep or Deep Sleep depending on the SLEEPDEEP control bit value. This provides a software mechanism to enter low power state.
When a wakeup interrupt or reset occurs, the Cortex-M3 will transition from Sleep or Deep Sleep mode back to Active mode. The wakeup interrupt is handled to service the associated event or peripheral.
The WFE (Wait For Event) instruction causes entry to Standby mode. In Standby only the backup power domain remains powered on. The chip exits Standby mode on a reset or external wakeup event.
Power Optimization Tips
Here are some tips to optimize power consumption in a Cortex-M3 system:
- Use Sleep or Deep Sleep modes when idle to disable clocks
- Configure GPIO and peripherals for lowest power
- Minimize external memory accesses
- Manage clocks, enable only when required
- Disable unused peripherals
- Use most efficient instruction sequences
Using Sleep and Deep Sleep low power modes allow disabling clocks and powering down unused modules. Configure GPIO pins for lowest drive strength and peripherals like ADC for low-power mode.
Optimize code to minimize accesses to external flash/SRAM which consume more power. Manage clocks to enable only for the duration when a peripheral is being used. Disable unused peripherals completely to eliminate extraneous power consumption.
Efficient coding techniques like avoiding unnecessary branches, optimizing loops also improve power efficiency by reducing CPU cycles required for a task.
Summary
In summary, the Cortex-M3 processor provides flexible system power management capabilities through its different power modes, power control signals, PMU module, and wakeup interrupts. Using the sleep and deep sleep modes intelligently together with peripheral low power settings, clock gating, and interrupt-driven wakeup allows optimizing the power consumption of a system to precisely match its performance needs.
