The ARM Cortex-M3 processor has multiple low power or sleep modes that allow the system designer to minimize power consumption during periods of inactivity. Understanding the different sleep modes and how to properly configure the Cortex-M3 to enter and exit these modes is critical for building energy-efficient embedded systems.
Overview of Sleep Modes
The Cortex-M3 supports three main sleep modes with multiple sub-modes:
- Sleep Mode
- Deep Sleep Mode
- Deep Power Down Mode
In the regular Sleep mode, the CPU is powered off while the peripherals and RAM remain powered on. This allows for a fast wakeup time since the CPU state is preserved in RAM. Deep Sleep mode powers down more components like flash memory while still retaining RAM and peripheral state. Deep Power Down mode shuts down even more components of the chip resulting in the lowest power consumption but with higher wakeup latency.
The multiple sub-modes under each main sleep mode allow for fine-grained control over which specific peripherals or clock domains remain powered on. This lets the developer optimize for the lowest power consumption while still meeting the peripheral and wakeup latency requirements of the application.
The Sleep mode is the lightest sleep mode in the Cortex-M3. In this mode, the CPU is powered off after saving its context to RAM. The peripherals and RAM remain powered on so they can continue running and maintain their state.
Since RAM is still powered, the contents of the CPU registers along with the program counter and other key processor state information are retained. This allows for a very fast wakeup from Sleep mode since the CPU can resume execution from where it left off with little delay. Typically, wakeup from Sleep mode takes less than 5 microseconds.
Sleep mode provides a good balance between power savings and wakeup latency. CPU power consumption is minimized while still allowing peripherals to remain active. The fast wakeup time allows CPU processing to resume quickly when an interrupt occurs. This makes Sleep mode very useful for intermittent activity where peripherals may need to autonomously react to external stimuli while the CPU is inactive.
Entering Sleep Mode
To enter Sleep mode, the WFI (Wait For Interrupt) instruction can be executed by the CPU. This causes the processor to suspend execution and enter Sleep mode until a permitted interrupt is triggered. All processor state is preserved in RAM while peripherals and RAM remain active.
Here is an example code snippet to enter Sleep mode using WFI: // Enable interrupts __enable_irq(); // Ensure interrupting peripherals are setup // Enter Sleep mode __wfi();
Alternatively, Sleep mode can be entered by setting the SLEEPDEEP bit to 0 in the System Control Register (SCR) and then executing a WFI instruction. The CPU will then suspend execution in Sleep mode while waiting for the interrupt.
Exiting Sleep Mode
Sleep mode is exited when one of the permitted interrupts occur. This triggers the CPU to wake up and continue code execution from where it left off. The peripherals and RAM state are all preserved so program execution can resume seamlessly.
To allow interrupts to wake the processor from Sleep mode, the interrupts must have their priority set in the Nested Vectored Interrupt Controller (NVIC). The interrupt enable bits for each interrupt must also be set in the NVIC to permit that interrupt to trigger wakeup.
Besides interrupts, Sleep mode can also be exited by a reset event. The microcontroller subsystem will reset and execution will restart from the reset vector on wake up.
Peripherals in Sleep Mode
By default in Sleep mode, peripherals like GPIO, timers, watchdog timer, ADC, and serial interfaces remain powered on and can continue functioning. Their internal states are maintained. Peripherals that do not rely on the CPU like timers and ADC can operate autonomously while the CPU is suspended.
Certain peripherals like USB and high-frequency clocks may be disabled on entry to Sleep mode to save additional power. These can be selectively kept active as needed but at the expense of some increased power consumption.
Power Consumption in Sleep Mode
Sleep mode allows the Cortex-M3 processor and system to achieve reasonably low static power consumption while retaining the fast wakeups needed for some applications. Typical current draw in Sleep mode is around 100 uA for the Cortex-M3 core.
Exact power consumption depends on the operating frequency, peripheral activity, and the presence of wait states. Lower frequencies, inactive peripherals, and zero wait states will result in lower power consumption in Sleep mode.
Deep Sleep Mode
Deep Sleep mode takes sleep operation to the next level by powering down more components on the Cortex-M3 chip. This includes disabling the flash memory alongside the CPU. RAM is still retained in the powered on state. This allows even lower power operation while still providing reasonably fast wakeups.
With flash memory powered off, code execution is suspended during Deep Sleep. So the processor state is stored in RAM rather than in flash. The contents of RAM are also preserved. Peripherals that do not require the flash or CPU can remain operational in Deep Sleep mode.
Entering Deep Sleep Mode
To enter Deep Sleep mode, the SLEEPDEEP bit must be set to 1 in the SCR register. This enables the deeper sleep state. The WFI instruction must then be executed to suspend CPU operation. // Set deep sleep bit SCR->SLEEPDEEP = 1 // Execute WFI __wfi()
Setting the SLEEPDEEP bit allows the Cortex-M3 to control whether the sleep state is shallow (regular Sleep mode) or deep (Deep Sleep mode). The WFI instruction triggers entry into the sleep state configured by SLEEPDEEP.
Exiting Deep Sleep Mode
Interrupts can wake up the CPU from Deep Sleep mode. The wake up time is longer than regular Sleep mode since flash memory needs to be reactivated. A reset event can also wake the processor from Deep Sleep.
When waking up from Deep Sleep, execution resumes from the point where the WFI instruction was executed. The processor state is restored from RAM since flash memory was unavailable in Deep Sleep. Program code execution resumes from flash once it is powered back on.
Peripherals in Deep Sleep
Since flash memory is disabled in Deep Sleep mode, peripherals that rely on it like the USB controller cannot remain active. Timers, GPIO, watchdog timer, ADC, and serial interfaces can stay operational if they do not depend on flash access. This allows autonomous peripheral activity to continue while in Deep Sleep.
SRAM and register contents are preserved so peripheral configurations are maintained in Deep Sleep. When waking up, peripherals can resume functioning as if they were never powered down.
Power Consumption in Deep Sleep
By disabling power hungry components like flash memory, Deep Sleep mode allows lower power consumption than regular Sleep mode. Typical currents can be in the range of 15-30uA range for Cortex-M3 systems in Deep Sleep mode.
Exact figures will vary based on the specific peripherals left on, operating frequency, presence of wait states and other factors. Inactive peripherals and faster wakeups generally need higher frequencies and supply voltages which consume more power.
Deep Power Down Mode
The Deep Power Down mode takes the Cortex-M3 into its lowest power sleep state. In this mode, the power supply to the entire chip is essentially turned off except for a small always-on domain. This keeps power draw at an absolute minimum but has consequences of loss of state and longer wakeup times.
In Deep Power Down mode, RAM contents are lost since memory power is disabled. Peripherals and I/O states are also reset. This mode is useful for shutting down unused circuits over long idle periods to conserve power.
Entering Deep Power Down Mode
To enter Deep Power Down mode, the DEEPSLEEP bit must be set to 1 in the SCR register. This enables the deepest system sleep state possible. The processor is then put to sleep using the WFI instruction. // Enable deep power down SCR->DEEPSLEEP = 1; // Execute WFI __wfi();
Setting the DEEPSLEEP bit gives the Cortex-M3 controller the capability to power down the entire system. WFI triggers entry into this mode when DEEPSLEEP is set.
Exiting Deep Power Down Mode
Since RAM and peripheral states are lost in Deep Power Down mode, the microcontroller effectively performs a full reset on wakeup. The reset handler executes and systems reinitialize from scratch. This resume process takes much longer than regular Sleep or Deep Sleep modes which retain memory and peripheral contexts.
Wakeup sources are limited to reset pin assertion or power-on reset activation in Deep Power Down mode due to the loss of state. Primary reset sources like the watchdog timer require initialization which cannot occur autonomously without CPU execution.
Peripherals in Deep Power Down
No peripherals retain state or remain active in Deep Power Down mode. RAM, flash memory, and all peripherals have their power supply disabled. So internal processor state is completely reset on wakeup from Deep Power Down mode.
Power Consumption in Deep Power Down
Deep Power Down mode minimizes static power consumption to just the tiny always-on power domain. Supply current can be in the single digit uA range or less, allowing extensive power savings during long inactive periods.
The tradeoff is much higher wakeup latency and complete loss of system state requiring a full reboot. For intermittent wakeups, Deep Power Down mode current draw averages out to very low levels due to extensive powered off time.
Choosing the Right Sleep Mode
The Cortex-M3 sleep modes provide a spectrum of options between minimizing power consumption and retaining system state and wakeup performance. Here are some guidelines for choosing the right mode:
- Regular Sleep mode offers the fastest wakeups while still reducing power. Use this when peripherals need to remain active and process state needs to be quickly restored.
- Deep Sleep mode minimizes power consumption while retaining RAM and peripheral states. Fastish wakeups are still possible. Useful when flash memory access is not required during sleep periods.
- Deep Power Down mode is for maximizing power savings during extended inactive times. The tradeoff is slow wakeups and full system re-initialization. Plan for appropriate wakeup sources.
Within each sleep mode, optimize peripherals, clocks, and voltages to meet the desired power and performance objectives. Measure power profiles using energy measurement ICs to validate and fine-tune configurations.
Sleep Mode Programming
Here are some best practices for programming the Cortex-M3 sleep modes:
- Use the WFI instruction to enter sleep rather than using Wait For Event (WFE). WFE has some overhead than can consume more power.
- Ensure unused peripherals, clocks, and hardware are properly disabled before sleep to minimize currents.
- Use sleep modes in idle loops or extended timeouts to maximize power savings.
- Configure permitted wake up sources like interrupts properly for each sleep mode.
- Initialize peripherals and restore program state on wakeup in Deep Power Down mode.
- Measure power consumption in different modes using ammeters to identify optimization opportunities.
With careful coding, sleep modes allow Cortex-M3 systems to achieve ultra low power operation without compromising performance during active periods. Combine sleep modes with other techniques like clock gating and voltage scaling to further reduce power consumption.
The Cortex-M3 sleep modes give embedded developers extensive control over the power consumption profile of their system. Regular Sleep mode provides fast wakeups for intermittent activity with peripheral processing. Deep Sleep mode further reduces power by disabling flash memory while retaining RAM and peripheral state. Finally, Deep Power Down mode maximizes power savings but incurs overhead of slower wakeups and system re-initialization.
Choosing the right low power mode requires analyzing the performance and latency constraints of the application versus the power budget. Optimizing peripherals, clocks, voltages and software is also needed to minimize the currents in each mode. With the right design approach, Cortex-M3 sleep modes enable energy-efficient embedded products with long battery life.