SPI Memory Interfaces vs Memory Mapped Memories in Arm Cortex

SPI and memory mapped memories are two different ways to connect external memories to Arm Cortex processors. The choice between them depends on the application requirements and tradeoffs between complexity, performance, and flexibility.

Overview of SPI

The Serial Peripheral Interface (SPI) is a synchronous serial interface commonly used to connect external peripherals and memories to microcontrollers and other devices. Here are some key points about SPI:

• SPI uses a master-slave architecture with one master device and one or more slave devices.
• The master controls the SPI bus and generates the clock signal SCK which synchronizes data transfer.
• SPI uses four logic signals – SCK, MOSI, MISO and SS (slave select).
• Data is shifted in and out serially via the MOSI and MISO lines one bit at a time.
• The SS signal selects which slave device the master talks to.
• Typical SPI speeds range from 1 Mbps to over 50 Mbps.
• SPI communication minimizes pins and complexity but is slower than parallel interfaces.

In summary, SPI provides a simple serial communication interface to connect low-speed external devices using a minimum of pins.

SPI Interfaces for External Memories

Here is how SPI is typically used to interface external memories with Arm Cortex MCUs:

• The MCU acts as an SPI master and the memory acts as an SPI slave.
• The memory is selected using an SS pin from the MCU.
• The SCK, MOSI and MISO pins are connected between the MCU and memory.
• Reads and writes are done by sending appropriate commands serially over SPI.
• High speeds like SDR50 and DDR50 are used for fast data transfers.
• SPI flash and SPI RAM chips often include a small SRAM buffer for caching.
• Transactions have protocol overhead like command, address, dummy cycles.

SPI memories enable adding more memory capacity to a system easily. But the sequential access and protocol overhead can limit performance.

Overview of Memory Mapped Memories

Memory mapped memories refer to external memories that are directly mapped into the processor’s memory address space. Here are some key aspects:

• The external memory is assigned a region in the MCU’s memory map.
• The MCU directly connects to the memory via a parallel interface.
• External memory is accessed just like internal memory with standard load/store instructions.
• No special commands are needed – the MCU drives address and control signals directly.
• Allows random access and execution in place (XIP).
• Interface can be 8-bit,16-bit or 32-bit wide depending on bandwidth needed.

In summary, memory mapped external memories are accessed just like internal memories by the Cortex MCU for maximum performance.

Memory Mapped Interfaces

Here are some common parallel bus interfaces used to connect external memory mapped memories to Arm Cortex MCUs:

• External Bus Interface (EBI)
• External Memory Controller (EMC)
• Parallel Memory Interface (PMI)
• Flexible Memory Controller (FMC)
• Octal SPI controller

The EBI, EMC, PMI and FMC are different flavors of parallel buses with address, data, and control signals to connect external memories. Octal SPI uses 8 data lines instead of 1 to get higher bandwidth compared to normal SPI.

Tradeoffs Between SPI and Memory Mapped Memories

Here are some key tradeoffs between using SPI memory interfaces versus memory mapped parallel interfaces:

• Interface complexity – SPI needs fewer pins and logic than parallel memory mapped bus.
• Memory capacity – Larger memories can be connected via memory mapped bus compared to SPI.
• Performance – Memory mapped memories provide higher bandwidth and low latencies.
• Random access – Memory mapped memories allow random accesses unlike SPI.
• Execution in place – Code execution directly from an external memory requires memory mapped interface.
• Board design – SPI needs fewer PCB traces, easier routing than memory mapped bus.
• Power consumption – SPI uses less power compared to parallel memory interfaces.

In summary, SPI provides a simpler, lower power interface, while memory mapped parallel bus enables better performance and capabilities.

Example Scenarios Comparing SPI and Memory Mapped Memories

Here are some example scenarios comparing the use of SPI versus memory mapped memories:

Boot Memory

• SPI flash used as boot memory – small size but low pins.
• Parallel NOR flash for boot – can execute code directly with good performance.

External RAM

• SPI RAM for smaller memories and lower speed access.
• Memory mapped parallel RAM for large capacity and high speed.

Storage Memory

• SPI flash for storage – lower speed, serial access.
• Parallel NAND flash for storage – high speed, random access.

Instruction Storage

• Cannot directly execute code from SPI flash.
• Parallel NOR/ROM allows direct execution in place.

In summary, factors like performance, flexibility, and resource requirements dictate the choice between SPI and parallel mapped interface.

SPI Memory Interfaces in Arm Cortex MCUs

Here are some examples of SPI memory interfaces in Arm Cortex MCUs:

• STM32F446 – Has support for SPI flash memories.
• NXP LPC4088 – Allows interfacing SPI flash and SPI RAM.
• Microchip SAMV71 – Supports SDR/DDR with SPI flash.
• NXP iMXRT1050 – Contains OCTOSPI for faster external memories.
• Cypress PSoC6 – Allows interfacing SPI NOR flash.

In these MCUs, the SPI peripheral handles interfacing with SPI memories. It takes care of protocol commands, timing and bi-directional shifts. DMA is used to accelerate data transfers.

Memory Mapped Interfaces in Arm Cortex MCUs

Here are some examples of memory mapped interface implementations in Arm Cortex MCUs:

• Nordic nRF52840 – EBI allows connecting parallel RAM, ROM and flash.
• TI Tiva C TM4C123 – Has external bus interface to add SRAM.
• STM32F769 – FMC provides support for parallel NOR flash.
• NXP LPC54018 – Contains programmable memory interface for external memories.
• Microchip SAM V71 – EMC enables interfacing SDRAM and static memory.

In these MCUs, dedicated memory controller peripherals are used to interface with parallel external memories. They handle timing, control signals, address mapping and bus arbitration.

Design Guidelines for Optimal Use

Here are some design guidelines for optimal use of external SPI and memory mapped memories in Arm Cortex MCUs:

• Analyze application requirements for performance, flexibility and memory capacity needs.
• Select suitable MCU with memory interface capabilities matching use case.
• Plan board layout to support interface – optimize trace lengths, routes, termination.
• Utilize DMA to offload data transfers and improve throughput.
• Use multiple memory banks and peripherals to allow concurrent access.
• Partition application to take advantage of XIP from parallel memory if needed.
• Analyze power profiles for peripheral and memories to optimize power consumption.
• Leverage caching support in memories if available.
• Use memory access benchmarks to compare achievable performance.

Careful selection between SPI and memory mapped interface based on use case along with good PCB layout, firmware design and power optimization enables building high performance Arm Cortex systems utilizing external memories optimally.

Conclusion

In summary, SPI and parallel memory mapped interfaces both have their place for connecting external memories to Arm Cortex MCUs. SPI provides a simpler low speed serial interface using fewer pins, while memory mapped parallel bus enables high performance direct access. The tradeoffs between interface complexity, performance, flexibility, memory size, power and other factors dictate the optimal selection for a particular application. Proper hardware and firmware design is needed to maximize the benefits. Arm Cortex MCUs provide varied options for both SPI and parallel mapped interfaces to add external memories.