The Cortex-M3 processor includes a number of core peripherals that are mapped to reserved address ranges in the Private Peripheral Bus (PPB). These reserved address ranges ensure that the core peripherals do not conflict with any external peripherals that may be added to a Cortex-M3 system. Understanding these reserved address ranges is important for system configuration and software development.
Overview of PPB and Core Peripherals
The Cortex-M3 PPB connects the processor core to on-chip peripherals. It provides a separate bus from the system AHB bus used for external memory and peripherals. The PPB allows concurrent access to on-chip peripherals during external memory transactions.
The core peripherals included in the Cortex-M3 processor include:
- Nested Vectored Interrupt Controller (NVIC)
- System Control Block (SCB)
- Memory Protection Unit (MPU)
- Embedded Trace Macrocell (ETM)
- Data Watchpoint and Trace Unit (DWT)
- Instrumentation Trace Macrocell (ITM)
- Flash Patch and Breakpoint Unit (FPB)
- Floating Point Unit (FPU)
- System timer, SysTick
- PLL, real-time clock (RTC), and backup registers
These core peripherals are essential for the functioning of the Cortex-M3 system and are mapped to reserved address ranges on the PPB. The address ranges ensure that the core peripherals do not conflict with any external peripherals added in a particular system implementation.
NVIC Address Range
The NVIC peripheral is mapped to the address range 0xE000E000 – 0xE000EFFF on the PPB. This address range is reserved for the NVIC registers. The NVIC is responsible for exception and interrupt handling in the Cortex-M3 system. The NVIC registers allow configuration of interrupt and exception priorities and control the processing of interrupts and exceptions.
Key NVIC Registers
- Interrupt Set Enable (ISER) – enables interrupts
- Interrupt Clear Enable (ICER) – disables interrupts
- Interrupt Set Pending (ISPR) – sets pending status of interrupts
- Interrupt Clear Pending (ICPR) – clears pending status of interrupts
- Vector Table Offset (VTOR) – sets position of exception vector table
- Application Interrupt/Reset Control (AIRCR) – controls reset, priority grouping, exceptions
- System Control Register (SCR) – configures fault handling
- Priority registers – set priorities of exceptions/interrupts
These NVIC registers allow complete configuration and control of interrupt handling in the Cortex-M3 system. The fixed NVIC address range ensures software can access these registers to manage interrupts and exceptions.
SCB Address Range
The System Control Block peripheral is mapped to address range 0xE000ED00 – 0xE000ED8F on the PPB. This range is reserved for the SCB registers that configure and control the system, including:
- CPUID – CPU ID register
- ICSR – Interrupt Control and State
- VTOR – Vector Table Offset
- AIRCR – Application Interrupt and Reset Control
- SCR – System Control Register
- CCR – Configuration and Control
- SHPR – System Handler Priority
- SHCSR – System Handler Control and State
- CFSR – Configurable Fault Status
- HFSR – HardFault Status
- DFSR – Debug Fault Status
- MMFAR – MemManage Fault Address
- BFAR – BusFault Address
- AFSR – Auxiliary Fault Status
The SCB registers allow configuration of the processor core, fault handling, system control, and interactions between software and hardware components. Fixing the SCB address range reserves these vital registers.
MPU Address Range
The Memory Protection Unit peripheral registers are mapped to address range 0xE000ED90 – 0xE000EDFF on the PPB. The MPU is used to implement memory protection and access control schemes. The main MPU registers include:
- MPU Type – MPU Type Register
- MPU Control – MPU Control Register
- MPU Region Number – MPU Region Number Register
- MPU Base – MPU Region Base Address Register
- MPU Attributes – MPU Region Attribute and Size Register
- MPU Base1 – MPU Alias 1 Region Base Address Register
These registers allow configuration of up to 8 protected memory regions with customized access permissions. The fixed MPU address range reserves space for this important peripheral.
ETM and DWT Address Ranges
The Embedded Trace Macrocell and Data Watchpoint and Trace unit provide tracing and debugging capabilities in the Cortex-M3 system. The ETM address range on the PPB is 0xE0041000 – 0xE0041FFF. This reserves space for the ETM configuration registers and FIFO.
The DWT address range on the PPB is 0xE0001000 – 0xE0001FFF. This reserves registers like the DWT Control Register, DWT Comparators, and DWT Exception and Program Counter Sample Register used for watchpoints and tracing.
Fixing the ETM and DWT address ranges reserves the space needed for their memory-mapped registers. This allows debug agents and software to access these registers to enable tracing and debugging.
ITM and FPB Address Ranges
The Instrumentation Trace Macrocell address range on the PPB is 0xE0000000 – 0xE0000FFF. The ITM provides support for printf style debugging through a FIFO mapped to this address range. Any writes to this address range get captured in the ITM FIFO without disrupting program flow.
The Flash Patch and Breakpoint unit address range on the PPB is 0xE0002000 – 0xE0002FFF. This reserves space for FPB registers like the Flash Patch Comparator Register used to enable flash patch functionality.
Reserving the ITM and FPB address ranges ensures software and tools can access the memory-mapped registers in these units to enable instrumentation tracing and flash patching capabilities.
FPU Address Range
The Floating Point Unit registers are mapped to address range 0xE000EF30 – 0xE000EF7F on the PPB. This range includes registers like:
- Floating Point Context Control Register
- Floating Point Context Address Register
- Floating Point Default Status Control Register
- Media and FP Feature Register 0
- Media and FP Feature Register 1
These FPU registers allow configuration of floating point context switching and status. The fixed FPU address range ensures consistent access to the FPU registers.
SysTick and Other Core Peripherals
The system timer SysTick registers are mapped to address 0xE000E010 – 0xE000E0FF on the PPB. This address range is fixed for the SysTick Reload Value Register, Current Value Register, Calibration Register, and Control and Status Register.
Several other core peripherals like the PLL, RTC, backup registers, and external bus interface are also mapped to small fixed address ranges on the PPB. Reserving these addresses ensures that software can reliably access these core peripherals.
External Device Address Mapping
The fixed address ranges reserved for the Cortex-M3 core peripherals only occupy a small part of the 4GB PPB address space. Most of the PPB address range from 0x40000000 to 0x5FFFFFFF remains available for mapping external peripherals in a particular system implementation.
So while external peripherals need to avoid the reserved addresses for core peripherals, they can utilize other areas of the PPB address space for memory-mapped registers. Vendor provided external peripherals will typically occupy addresses in the 0x40000000-0x5FFFFFFF range or higher.
Reference Manuals
For further details on the reserved address ranges for the Cortex-M3 core peripherals, refer to the following reference manuals from ARM:
- Cortex-M3 Devices Generic User Guide
- Cortex-M3 Technical Reference Manual
- Cortex-M3 Revision r2p1 Technical Reference Manual
- ARMv7-M Architecture Reference Manual
The reference manuals provide complete details on all reserved memory mapped registers in the Cortex-M3 PPB address space.
Summary
In summary, the Cortex-M3 processor includes a number of core peripherals that are mapped to reserved address ranges on the Private Peripheral Bus. Reserving these PPB address ranges prevents conflicts between core and external peripherals and provides software with fixed addresses to access the registers of core peripherals.
Understanding the reserved address ranges for NVIC, SCB, MPU, ETM, DWT, ITM, FPB, FPU, SysTick, and other core peripherals is key to proper software development and system configuration with Cortex-M3 processors.
