Upgrading from the older Cortex-M0 to the newer Cortex-M0+ microcontroller can provide several benefits for devices and systems needing an extra performance boost. The Cortex-M0+ architecture builds on the strengths of the original Cortex-M0 design while adding some key enhancements. When considering an upgrade, there are a few key factors to take into account to ensure a smooth transition.
Performance Improvements
The most notable upgrade with the Cortex-M0+ is the improved CPU performance. The M0+ boosts clock speeds up to 50% higher compared to the original M0. This speed boost is achieved thanks to pipelining enhancements in the microarchitecture. The M0+ can execute up to 2 instructions per clock cycle, whereas the M0 was limited to just 1 instruction per cycle. This pipelining optimization reduces wasted cycles and improves throughput.
In addition to the faster clock speeds, the M0+ also includes an optional hardware multiplier, which can execute multiply operations in a single cycle. The original M0 lacks a hardware multiplier, meaning multiply operations take multiple cycles to execute in software. The dedicated multiplier block frees up the CPU and speeds up math-heavy code considerably.
Power Efficiency
Despite the performance improvements, the Cortex-M0+ actually consumes less active power than the older M0 core. The M0+ achieves this thanks to advanced circuit techniques and smarter power gating of unused logic blocks. In active mode, the M0+ uses about 10% less power clock-for-clock compared to the M0.
The M0+ also supports an optional sleep deep power-down mode for ultra low leakage currents. This helps reduce power draw to just 0.57μA per MHz, around 2X lower than the M0. For power-constrained devices like IoT sensors running on batteries, the power savings can extend battery life significantly.
Memory and Peripherals
A key factor when upgrading is maintaining compatibility with existing memory maps and peripherals. The good news is the Cortex-M0+ maintains nearly identical memory and peripheral operation compared to the older M0. The M0+ integrates with the same Cortex-M0 NVIC, SysTick timer, GPIOs and debug components. This makes integration with existing chip designs straightforward.
The M0+ does allow some flexibility for memory and bus interface upgrades. The M0+ supports up to 512KB of flash memory, up from 256KB on the M0. SRAM is increased to 64KB from 32KB as well. The M0+ also introduces bit-banding support, allowing single bit accesses to memory mapped peripherals while only using byte or half-word reads/writes on the bus.
Toolchain and Code Compatibility
The good news on the software side is that code written for the Cortex-M0 will work without any changes on the M0+. This makes porting software over to the new core a relatively simple process. The M0 and M0+ utilize the same ARMv6-M Thumb instruction set architecture, so existing object code will function normally.
The toolchain is also identical, with GNU ARM Embedded toolchains like GCC supporting both M0 and M0+ with the same compile options. IDEs like Keil MDK merely require choosing the new M0+ target when compiling projects. This makes code migration transparent in most cases.
Pin Compatibility Constraints
A key consideration when upgrading the microcontroller core is maintaining pin compatibility with the existing M0 design. The good news is the M0+ maintains nearly identical pin-to-peripheral mappings, making PCB layout changes minimal. However, there are some subtle differences to keep in mind.
For one, the M0+ uses a higher 1.8V core voltage, compared to 1.65V for the M0. Level shifters may be needed on digital I/O pins to account for this. The M0+ also requires an external 32kHz clock if using the low-power timer option. Finally, the optional hardware multiplier uses 2 additional pins not present on the M0.
With careful planning, most upgrades can manage with the same PCB layout. But new board spins may be required if the pin changes impact critical routings. This is an important consideration for upgrades being done mid-lifecycle on existing products.
Interrupt Latency
One subtle but important specification that can impact real-time performance is interrupt latency. This refers to the time delay from an interrupt being asserted to the instruction being executed by the CPU.
The pipelining enhancements in the Cortex-M0+ lengthen this latency slightly compared to the M0. The M0+ has a best-case latency of 4 clock cycles, whereas the M0 has a 3 cycle minimum latency. This pipeline delay must be accounted for when migrating time-sensitive applications.
Real-Time Guarantees
For systems relying on hard real-time task deadlines, the Cortex-M0+ maintains the same reliable real-time operation as the M0. Worst-case interrupt latencies using CMSIS standards only differ by 1 clock cycle. The regular pipeline structure also ensures consistent timing of instructions.
Overall, real-time performance is comparable between M0 and M0+. But additional validation may be required for systems with microsecond-level task deadlines to account for the extra cycle of latency. Stress testing with worst-case interrupts patterns can verify real-time deadlines are still met.
Debug and Trace
An often overlooked aspect of microcontroller upgrades is maintain compatibility with debug and trace capabilities. The Cortex-M0+ maintains support for ARM’s embedded trace macrocell (ETM) for instruction and trace data. It also supports hardware breakpoints and watchpoints for debugging.
The only change in debug support is a third watchpoint comparator, up from two on the M0. So debugging capability is actually improved slightly. No changes to JTAG debug probes are required when upgrading to the M0+ core.
Software Migration Costs
A final factor to consider is the software migration effort required to move over to the upgraded microarchitecture. The good news is the Cortex-M0 and M0+ present nearly identical functionality to the programmer. So software migration costs are minimal in most cases.
The main software task is recompiling source code for the new device header files and M0+ target. Any memory locations or hardware peripherals that changed addresses will require code tweaks. Also, interrupts latencies may need adjustment for hard real-time tasks.
Overall the software migration effort is relatively small thanks to the compatibility between the M0 and M0+ cores. Much of the existing firmware codebase can be reused without significant changes required.
Conclusion
Upgrading from legacy Cortex-M0 designs to the newer Cortex-M0+ can provide meaningful performance and power efficiency improvements. But smooth integration requires evaluating pin compatibility, real-time guarantees, debug support, and software migration costs. With careful planning, most existing M0 designs can upgrade to M0+ without extensive board or software changes. The process allows squeezing extra performance and battery life out of proven designs.
