When debugging ARM Cortex-M1 chips using the KEIL ULINK2 debugger, users may encounter various issues that prevent effective debugging. The Cortex-M1 is one of the early ARM cores designed for microcontrollers and relies on ARM’s v6-M architecture. While dated, Cortex-M1 chips are still found in some legacy and commercial devices. The KEIL ULINK2 is a popular JTAG/SWD debugger from Arm’s software division that supports Cortex-M debugging. However, there are some specific problems users can run into when trying to debug Cortex-M1 chips with ULINK2.
ULINK2 firmware limitations
One major issue is that the ULINK2 firmware has limited support for Cortex-M1 debugging. The debugger was designed more for newer Cortex-M3 and M4 chips. As such, some Cortex-M1 specific debug features may not work properly or at all on ULINK2. For example, users may find single-stepping is unreliable, watchpoints are not triggering correctly, or memory reads fail. The ULINK2 firmware needs to implement the debug architecture specifics of the Cortex-M1 for robust debugging. Unfortunately, Arm does not seem to have added full Cortex-M1 support to the standard firmware. Users may need to request or develop custom firmware with improved Cortex-M1 debugging compatibility.
JTAG vs SWD issues
Another problem stems from the debug interface used. Modern Arm chips use the two-pin SWD interface which is faster and uses fewer pins than the legacy 5-pin JTAG interface. However, Cortex-M1 devices may only implement an older JTAG interface. The ULINK2 supports both SWD and JTAG debugging. But users often encounter issues when trying to use SWD debugging on Cortex-M1 targets that only have JTAG hardware. Symptoms include the debugger failing to correctly identify the target chip or reporting incorrect device IDs. The solution is to force the ULINK2 into JTAG mode to match the debug interface on the target board or chip. This may require changing debugger settings and target board jumpers. Consult the device datasheet and ULINK2 manual for proper JTAG configuration.
SUB GHz clock speeds
The Cortex-M1 core is capable of operating at very low clock speeds under 1 GHz. In fact, some Cortex-M1 microcontrollers run at just 32 kHz for real-time functions. However, the ULINK2 may have issues debugging chips below 1 MHz. The debugger itself requires a higher clock frequency. There can be problems establishing a debug connection at very low chip frequencies. Users may need to temporarily increase the Cortex-M1 clock speed during debugging. If the chip clock is not adjustable, an alternate debugger may be required. For best results, the target chip speed should be kept above 1 MHz when using the ULINK2 for debugging sessions.
Another common issue with debugging Cortex-M1 chips is running into breakpoint limitations. The Cortex-M1 CPU core supports only 4 breakpoint registers for breakpoints and watchpoints. In comparison, newer cores like the Cortex-M3 support up to 16 breakpoints. The ULINK2 further limits simultaneous breakpoint use during debugging. Depending on the firmware and API used, the ULINK2 may support 4 or less breakpoints. This can severely restrict debug abilities on an already limited Cortex-M1 target. Workarounds include carefully prioritizing watchpoint use or developing creative ways to trigger program halts without breakpoints. But fundamentally, the Cortex-M1 and ULINK2 combination lacks robust breakpoint support offered on newer ARM chip debuggers.
Small code size issues
Cortex-M1 chips are designed for simple microcontroller applications and can only support small programs. The limited Cortex-M1 flash size poses a problem when debugging with ULINK2. Modern debuggers utilize onboard code to facilitate debugging sessions. The ULINK2 may attempt to run larger onboard code routines that exceed the Cortex-M1’s size constraints. Users have reported issues downloading ULINK2 stub code into small Cortex-M1 flash sizes. Possible solutions include reducing the ULINK2 stub size, locating it in target RAM rather than flash, or using an external flash chip. But fundamentally, small Cortex-M1 code sizes mismatches the ULINK2 assumptions of larger program capacity.
Target power supply problems
Finally, device power issues can also affect ULINK2 and Cortex-M1 debugging. The ULINK2 requires the target device to be sufficiently powered during debug operations. However, Cortex-M1 chips may run on very low power or intermittent supply voltages. The debug interface can fail if the chip resets or browns out during debugging due to insufficient power. Users should provide a clean and stable power source to the target hardware while debugging. Level shifters may be needed to tolerate any voltage mismatches between the ULINK2 and Cortex-M1 device. The ULINK2 needs accurate target power to successfully interface with the Cortex-M1 debug port.
Workarounds and solutions
Despite the challenges, users still have options to debug Cortex-M1 chips with the ULINK2. The first step is verifying debugger and target board hardware are configured properly for JTAG/SWD debugging. Double check pins connections, voltage levels, and pull-up resistors on debug lines. Ensure the ULINK2 has the latest firmware and debugger software. Setting the ULINK2 to multi-drop JTAG mode can improve reliability for some chips. Target power supplies require special attention to keep the chip alive during debugging.
Software can also help overcome hardware limits. Debugging code can be optimized to operate within the Cortex-M1 size and breakpoint constraints. Changing debugger options may reduce stub sizes and avoid hardware issues. At the extreme, users may need to develop custom ULINK2 firmware that is Cortex-M1 compatible. An alternate debugger designed specifically for Cortex-M1 debugging is another option if ULINK2 issues persist.
In summary, the Cortex-M1 and ULINK2 have fundamental mismatch in terms of architecture, speed, size, and interfaces. Users may need to apply hardware and software workarounds to achieve acceptable debugging. However, the right configuration and optimization can allow the popular ULINK2 to debug most Cortex-M1 targets. With some effort, the limitations can be mitigated or avoided completely.