The short answer is yes, it is possible to port the DesignStart Eval design to a different FPGA development board than the one it was originally targeted for. However, it requires some effort and hardware expertise to make the necessary modifications. The feasibility and level of difficulty will depend on how compatible the new target board is with the original one. Factors like FPGA chip family, clocking, interfaces, and more will determine how challenging the porting process is.
Overview of the DesignStart Eval Board and Design
First, let’s provide some background. The DesignStart Eval board is an FPGA development board launched by ARM in 2020. It features a Xilinx Artix-7 FPGA along with peripherals like USB, Ethernet, accelerometer, buttons, LEDs, and more. ARM provides a reference design targeting this specific Eval board that demonstrates how to integrate a Cortex-M1 CPU inside the Artix-7 FPGA fabric.
The reference design includes the Cortex-M1 CPU subsystem, peripherals, memory interfaces, and glue logic needed to connect and run on the Eval board. It’s optimized for that particular set of components. Both the hardware and software are tailored to work with each other.
Factors that Determine Portability
When porting this reference design to a new FPGA development board, there are several hardware considerations:
FPGA Device Family
The Xilinx Artix-7 FPGA on the original Eval board belongs to the 7-series FPGA family. If the new board has a compatible 7-series FPGA or an FPGA from the same technology generation, porting will be simpler. The design would require more significant changes if moving to a newer generation like UltraScale or UltraScale+.
Clocking Structure
The clocking architecture and frequencies supported by the new FPGA must match the requirements of the DesignStart design. This includes clocks for the Cortex-M1 subsystem, peripherals, interfaces like DDR memory controller, and any board-level clocks.
External Interfaces
Any external interfaces used in the design like Ethernet, USB, SPI, etc. must be available on the new board. Ideally the PHY devices should be the same or very similar. Differences in timing, signaling levels, or protocols would necessitate logic modifications.
Memory Configuration
The amount, type, and configuration of memory available on the new board must meet the minimum requirements of the reference design. This includes specifications for the DDR2/DDR3 memory controller and SRAM interfaces.
Peripherals
Peripheral interfaces like GPIO, LEDs, switches, accelerometer and their electrical characteristics should closely match. Else the logic that interfaces with them requires changes.
Toolchain Compatibility
The ported design would need to be compiled with the toolchain supported by the new FPGA board, which depends on the FPGA vendor and family. So the project would require migrating to the appropriate toolchain. For example, moving from a Xilinx 7-series board to an Intel (formerly Altera) board.
Steps for Porting to a New Board
At a high level, these are the typical steps for porting the DesignStart reference design to a new FPGA development board:
- Select a target board with an FPGA that can support the hardware requirements discussed earlier.
- Create a new Vivado or Quartus project targeting this board.
- Import the RTL source files, IP cores, constraints, etc. from the original project.
- Make FPGA pin assignments compatible with the new board schematics.
- Modify clocking constraints to match the new board.
- Update memory controller configurations if needed.
- Modify board-dependent logic like I/O interfaces.
- Resolve any toolchain-related issues.
- Verify ports and connections between IP cores and logic.
- Fix timing closure issues revealed during implementation.
- Validate functionality via simulation and hardware testing.
Throughout the process, replication of the original timing constraints and design structure should be attempted as much as possible. The goal is to preserve the behavior while adapting to the new target. With careful planning and effort, it’s possible to successfully port most key functions. Complete pin-for-pin compatibility is unlikely, but the Cortex-M1 subsystem can be made functional.
Example Scenario: Porting to a Xilinx KC705 Board
To make this more concrete, let’s consider an example scenario. Say we want to port the DesignStart reference design to a Xilinx KC705 demo board instead of the Eval board. This board features a Xilinx Kintex-7 FPGA, so it is from the same family. However, it has a different package, periphery, and interfaces. How feasible is this port?
The good news is that since both boards have a 7-series Xilinx FPGA, the DesignStart logic, IP cores, and RTL should synthesize fairly smoothly. The existing XDC constraints provide a starting point that can be adapted for the KC705 clocks. The KC705 has dual DDR3 instead of DDR2, but it is still supported by the memory controller with some configuration tweaks.
On the more challenging side, the accelerometer and USB PHY would need replacement since the KC705 lacks those. New logic would need to be developed to interface with the KC705 peripherals like the ADC, audio codec, SRAM, etc. The KC705 also has PCIe which is unused. Modifications would be needed to ensure timing closure due to the different speed grade and package.
With work, a functioning port should be achievable. But it will take time and hardware design expertise. For a hobbyist unfamiliar with the FPGA tools, this would be an ambitious project. It is certainly possible, but the feasibility depends greatly on the porting team’s skills and how compatible the boards are.
When Starting from Scratch Makes More Sense
In some cases, trying to port the existing DesignStart design may be too difficult or even ill-advised. If the new board has an FPGA from a totally different family or vendor, it likely makes more sense to start from scratch. Developing a new design using the IP blocks, peripherals, and constraints tailored to that board would be less effort than forcing a square peg into a round hole. For very significant architectural differences, porting reaches a point of diminishing returns.
Conclusion
Porting FPGA designs between boards is certainly possible but also challenging. For the DesignStart Eval design, porting to another similar 7-series Xilinx board like the KC705 should be achievable with concerted effort. But attempting to port to a completely different FPGA family or vendor may not be worth the effort required. The closer the boards are in specifications, the more feasible porting becomes. With careful planning and sufficiently skilled engineers, the DesignStart design can likely be migrated to a compatible board as long as timing, tools, IP cores, interfaces, and other factors are addressed.
