ARM Cortex processors can operate in either little endian or big endian mode. The endianness is configurable in software, so ARM Cortex supports both endian formats. This gives developers flexibility in choosing the appropriate endianness for their application.
What is Endianness?
Endianness refers to the order in which bytes are arranged in computer memory for representating data. There are two types of endianness:
- Little endian – The least significant byte is stored at the lowest memory address. Mainly used by Intel x86 processors.
- Big endian – The most significant byte is stored at the lowest memory address. Used by many RISC processors.
For example, the 32-bit hexadecimal number 0x12345678 would be stored in memory as follows:
| Memory Address | Little Endian | Big Endian |
|---|---|---|
| 0x100 | 0x78 | 0x12 |
| 0x101 | 0x56 | 0x34 |
| 0x102 | 0x34 | 0x56 |
| 0x103 | 0x12 | 0x78 |
As you can see, the byte order is reversed between little endian and big endian formats. This byte order difference needs to be handled appropriately when transmitting data between systems using different endianness.
Endianness in ARM Cortex
ARM Cortex processors are based on the ARM instruction set architecture, which supports both little endian and big endian operation. The ARMv6 and later architectures included instructions to allow switching between endianness in software.
Here are some key points on endianness support in ARM Cortex CPUs:
- The default reset state for ARM Cortex is little endian for ARMv7 architecture based processors like Cortex-A8, Cortex-A9 etc.
- For older ARMv6 architecture based processors like Cortex-M0, Cortex-M3, the default reset state is configurable to little endian or big endian using configuration options.
- The SETEND instruction can be used to switch between little endian and big endian data access at runtime.
- The current endianness state is indicated by the EE bit in the CPSR (Current Program Status Register).
- Load and store instructions have variants to handle endian conversion automatically (LDRBE, STRBE etc).
- The ARM EABI (Procedure Call Standard) uses little endian format.
This flexible endianness support allows ARM Cortex processors to be used in systems that require either little endian or big endian operation. The endianness can be configured statically for the entire system, or changed dynamically by software when required.
Why Endianness Support is Important
Providing support for both little endian and big endian modes in ARM Cortex gives significant benefits:
- Interoperability – Data and code can be shared between ARM Cortex systems using different endianness, which helps in interoperability between components.
- Networking – Network packets often use big endian format. Native big endian support allows efficient networking on ARM.
- Legacy software – Older ARM based systems used big endian, so retaining big endian support enables legacy software to function.
- Performance – In some cases, little endian provides better performance. ARM Cortex allows choosing the optimal format.
- Vendor compatibility – Big endian matches the endianness of other vendor architectures like SPARC, POWER.
By supporting both big endian and little endian operation in hardware and software, ARM Cortex processors can be deployed in a wide range of use cases requiring different endian formats.
Examples of Endianness Configuration
Here are some examples of how endianness can be configured on ARM Cortex processors:
1. Cortex-M3 (ARMv7-M)
- Reset value of endianness is configured via the ACTLR.DISMCYCINT register bit.
- This sets the default reset state to little endian (0) or big endian (1).
- The SETEND instruction can then switch endianness at runtime if needed.
2. Cortex-A9 (ARMv7-A)
- Reset state is always little endian.
- Big endian operation can be enabled by setting the EE bit in CP15 register 1.
- This causes the next exception return to switch to big endian mode.
3. Cortex-M0 (ARMv6-M)
- Endianness is chosen at build time via compiler options.
- Big endian operation uses BE-32 format for instructions.
- Little endian uses LE-32 instruction format.
- The chosen format then applies for entire application.
So in summary, a combination of build time configuration options and runtime software instructions allow endianness to be set up as per requirement on ARM Cortex.
Impact of Endianness on Performance
The choice of endianness can impact performance in certain scenarios:
- Little endian works better for memory operands as the least significant bytes stored first match ARM’s native operand ordering.
- Big endian may provide faster processing when accessing external big endian formatted data.
- Frequent endianness switching can degrade performance slightly due to extra instructions.
- For networking loads, big endian reduces need for byte reordering.
- In some byte interleaving cases, little endian operates better due to存储顺序.
However, in general the performance differences are quite small. Endianness should be chosen based primarily on software requirements rather than performance considerations.
Usage of Endianness in Common ARM Systems
Here are some examples of endianness usage in common ARM Cortex based systems:
- Android OS – Uses little endian for ARMv7 Android devices as most apps assume LE format. But the byte order safe NDK allows supporting BE.
- Linux – Supports both endian formats. Distros like Debian default to LE while Fedora and Ubuntu support BE too.
- Windows RT – Defaulted to little endian for application compatibility, while also providing big endian driver support.
- iOS – Sticks to little endian format only for uniformity across apps.
- Nintendo Switch – Uses mixed endianness, with memory in LE but many registers being BE.
In summary, ARM Cortex processors are very flexible in their endianness support. This allows system and app developers to choose the appropriate byte ordering required for their use case.
Conclusion
To conclude, ARM Cortex CPUs support both little endian and big endian operation. The endianness mode can be chosen at build time or switched at runtime using configuration options and software instructions. Having dual endianness support provides ARM Cortex processors the flexibility to handle data in different byte orderings, making them suitable for a wide range of applications requiring certain endian formats. While endianness does not generally affect performance significantly, it enables interoperability and compatibility for networking, legacy software and multi-vendor systems.
