Connecting an ARM Cortex-M1 processor to an Altera FPGA using the Virtual JTAG interface can be a powerful technique for embedded systems designers. It allows the ARM processor to directly control the FPGA fabric and take advantage of hardware acceleration and flexible IO configuration options. However, interfacing the two requires an understanding of both the ARM and FPGA sides of the connection.
Overview of ARM Cortex-M1 and JTAG Interface
The ARM Cortex-M1 is a 32-bit RISC processor optimized for microcontroller applications. It has a streamlined instruction set architecture and efficient 3-stage pipeline allowing high performance at very low power consumption. The Cortex-M1 implements ARM’s v6-M architecture, which includes support for the ARM Debug Interface v5 (ADIv5), a standard debug and trace interface.
ADIv5 includes a JTAG interface for accessing on-chip debug components and performing boundary scan testing. JTAG (Joint Test Action Group) is a common standard that uses a dedicated 4-wire Test Access Port (TAP) for debugging and hardware testing purposes. The ARM JTAG interface provides full access to the processor’s internal registers, breakpoints, watchpoints, and other debugging features.
FPGA Virtual JTAG Overview
While physical JTAG ports are common, many modern FPGA devices also provide “virtual JTAG” interfaces over their general purpose IOs. This allows JTAG functionality without requiring a dedicated port and wires. The FPGA is configured to implement the JTAG state machine and signaling protocols on its IO pins.
For example, Altera (now Intel) FPGAs integrate a Virtual JTAG megafunction that can implement a JTAG interface compliant with the IEEE 1149.1 standard. The megafunction has configurable pins and options to match the JTAG ports on connected devices.
Interfacing ARM JTAG and Altera Virtual JTAG
Connecting the ARM Cortex-M1 JTAG with Altera Virtual JTAG requires interfacing their two TAP interfaces. This involves matching the JTAG timing and handshaking protocols between the two sides. It also requires deciding which device will act as the JTAG master and controller.
There are several approaches to consider when interfacing ARM JTAG with Altera Virtual JTAG:
- Use ARM device as JTAG master – the Cortex-M1 TAP controller acts as the master and clock source, Altera Virtual JTAG acts as slave
- Use Altera FPGA as JTAG master – Virtual JTAG TAP controller acts as master, ARM JTAG as slave
- Use bidirectional JTAG bridge – Allows either side to initiate JTAG transactions
The optimal choice depends on the overall system design and which device needs to initiate JTAG activities. Using the ARM as master allows it to control when debug activities occur. Using the FPGA as master allows more flexibility if multiple slave devices are present.
Configuring Altera Virtual JTAG Interface
The Altera Virtual JTAG interface is highly configurable to support different use cases. Key configuration options include:
- JTAG pins – Any IO pins can be assigned as TDI, TDO, TCK, TMS.
- Tap state machine – Handles the JTAG state transitions and signaling.
- IR register – Instruction register width, sets opcodes for test operations.
- TAP controller settings – TCK frequency, idle state high/low etc.
These parameters in the Altera megafunction can be tweaked to correctly interface with the ARM JTAG port width, pin mappings, and signaling requirements.
Interfacing ARM JTAG and Virtual JTAG State Machines
The JTAG state machines on the ARM and FPGA sides need to synchronize for proper handshaking. This may require asserting signals in a specific order during the state transitions to avoid stuck states. For example, the FPGA should not change TMS until TCK is high, and the ARM should sample TDO on rising TCK edges.
Managing the JTAG reset and transition between states like Test-Logic-Reset, Run-Test/Idle, and Shift-IR is key for getting the two TAP controllers to synchronize successfully.
Matching JTAG Clock Speeds
For reliable operation, the TCK clock frequencies between the ARM JTAG and Altera Virtual JTAG should match. The Altera megafunction has a maximum TCK frequency setting that should be aligned with the ARM JTAG TCK speed.
Using a buffered clock lane on the FPGA pin mapped to TCK can help reduce propagation delay and signal skew between the two JTAG domains.
Implementing Bidirectional JTAG Bridge
For a bidirectional JTAG connection, a device like RTSC’s ARMADILLO can act as a bridge. It can interconnect two JTAG ports and pass transactions between the masters in either direction.
The bridge needs to internally synchronize the two TAP controllers by buffering signals like TMS and TDI/TDO between the domains. This allows driving JTAG traffic in either direction across the bridge.
Careful FPGA pin planning and isolation is needed with a bidirectional bridge to avoid contention when the two JTAG masters are both active.
Typical ARM + FPGA JTAG Use Cases
Here are some common applications of connecting ARM JTAG and Altera FPGA Virtual JTAG:
- FPGA programming – ARM can act as master to control FPGA configuration and programming.
- ARM debug – FPGA accesses ARM JTAG as master to control debugging.
- System reset – Coordinate FPGA and ARM resets over JTAG.
- Firmware updates – ARM uses FPGA JTAG to update FPGA fabric firmware.
Other advanced uses like on-chip logic analyzer, cross-triggering, and multi-device debug are also possible by chaining the JTAG connections.
Verifying the ARM-FPGA JTAG Interface
To confirm correct operation of the ARM-FPGA JTAG interface, some basic validation tests can be performed:
- Initialize JTAG state machines on both devices and verify they can reach Test-Logic-Reset state.
- Perform basic JTAG enumeration of ARM TAP controller ID register.
- Verify ARM can successfully shift in test vectors and read back expected results.
- Run boundary scan chain test to confirm TDI-TDO connection.
- Test basic FPGA functionality like lights-out flash programming via ARM JTAG.
More robust system testing like multi-device boundary scans, cross-triggering, and complex debug workflows can follow these basic connectivity verifications.
Conclusion
Interfacing ARM Cortex-M class processors with Altera FPGAs via JTAG enables powerful embedded designs leveraging both technologies. Careful configuration of the Virtual JTAG interface and synchronizing it with ARM ADIv5 JTAG creates a seamless debug and programming environment.
With robust validation testing, ARM-FPGA JTAG connectivity can provide the foundational backbone for high-performance embedded systems.
