How to Set Up External SPI Memory with an ARM Cortex-M3?

Setting up external SPI memory with an ARM Cortex-M3 microcontroller provides additional non-volatile storage space for data and code. The key steps are configuring the SPI peripheral, connecting the memory chip, initializing the memory, and accessing it in software. With some configuration, external SPI memory can be used as executable program memory or for data storage.

Overview of Connecting External SPI Memory to a Cortex-M3

Most Cortex-M3 microcontrollers have at least one SPI peripheral that can be used to connect to an external SPI memory chip. The memory is connected using the SPI lines: SCK for clock, MOSI for Master Out Slave In data, MISO for Master In Slave Out data, and SS for slave select. The microcontroller acts as the SPI master, generating the SCK clock signal and driving MOSI when writing data. The memory device acts as the SPI slave, responding to the clock signal and driving MISO when reading data. An additional slave select line chooses the target slave device.

Standard SPI flash and EEPROM memory chips can be used, offering storage capacities from kilobytes to megabytes. Access times and clock frequencies will depend on the specific memory chip being used. The memory requires power and ground connections in addition to the SPI signals.

In software, the SPI peripheral of the Cortex-M3 must be initialized and configured. The slave select pin connected to the memory device can be chosen. Important parameters include setting the SPI mode, bit order, clock frequency, and chip select behavior. Once initialized, memory operations like read, write, and erase can be performed using the SPI peripheral.

For simple data storage, the memory can be accessed directly through the SPI interface. With some additional configuration, the external memory can also be used as executable program memory for the Cortex-M3. This allows larger and more complex programs to be stored and run from the external SPI memory.

SPI Communication Overview

The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol used for short distance communication between microcontrollers and peripherals. Devices operate in either Master or Slave mode. A master device uses separate lines for clock (SCK) and data (MOSI) output, and data (MISO) input from the slave device. The SCK clock generated by the master synchronizes the data transfer between the two devices.

SPI is a full duplex protocol, meaning data can be sent and received at the same time. This allows for high-speed synchronous communication between a master and a single slave or multiple slave devices. Individual slave select (SS) lines are used by the master to choose which slave device to communicate with.

The SPI master and slave devices must agree on communication parameters such as clock polarity and phase, clock rate, bit order, and word length. Once configured, SPI provides a simple serial interface with very high data rates. SPI is commonly used to connect microcontrollers to peripherals such as sensors, SD cards, and LCD displays.

Cortex-M3 SPI Peripheral Overview

Most Cortex-M3 processor implementations include at least one SPI peripheral that can connect to external devices using the SPI protocol. The SPI peripheral is capable of operating as either a master or a slave, but for connecting external memory the Cortex-M3 will be configured as the SPI master.

The SPI peripheral has a serial clock line output (SCK) and a Master Out Slave In data output line (MOSI). It also has a Slave Out Master In data input line (MISO) and multiple Slave Select outputs. The Cortex-M3 SPI peripheral has several registers that allow configuring parameters like clock rate, bit order, word length, and mode.

The SPI peripheral can manage communication with multiple external SPI slave devices. The slave select outputs allow choosing which slave device to access at any given time. Interrupts can be generated on SPI events to allow asynchronous SPI communication with minimal CPU overhead.

Setting up the SPI peripheral includes enabling the SPI module clock, configuring SPI pins for alternate function use, setting communication parameters, and initializing the peripheral. Once initialized, the SPI data register and control bits can be used to send and receive data to the external SPI slave memory device.

Selecting an SPI Memory Chip

There are many SPI compatible memory chips available for adding external storage to a Cortex-M3 system. Factors that determine which SPI memory to use include:

• Storage capacity – SPI memories range from 1 Kbit to 128 Mbit. Larger memories provide more storage but cost more.
• Voltage levels – Memories typically operate at 3.3V or 1.8V logic levels, matching common MCU power supplies.
• Access speed – Faster SPI clock rates allow quicker data access but require MCU support.
• Cost – More capacity and faster access increase memory chip pricing.
• Interface – SPI memories have an industry-standard pinout for easy interfacing.
• Power – Lower power chips reduce total system power consumption.

For a Cortex-M3 system, SPI flash and EEPROM chips from manufacturers like Winbond, Microchip, Cypress, and Micron provide good options for external memory. Multi-Mbit serial flash chips often provide the best balance of capacity, speed, and cost.

Connecting SPI Memory to a Cortex-M3

Interfacing an SPI memory chip to a Cortex-M3 requires connecting the SPI signals between the microcontroller and memory device. The following SPI signals need to be connected:

• SCK – Serial Clock from Cortex-M3 SPI peripheral provides timing for the interface.
• MOSI – Master Out Slave In data line, transfers data from Cortex-M3 to memory.
• MISO – Master In Slave Out data line, transfers data from memory to Cortex-M3.
• SS – Slave Select chooses target slave device for communication.

The memory will also require power and ground connections. Decoupling capacitors should be provided near the power pins of both the Cortex-M3 and memory chip. The SPI lines may require pull-up or pull-down resistors depending on signal levels.

A single Cortex-M3 SPI peripheral can support multiple external SPI slave devices. Individual SS lines are used to select each slave device. The SPI clock and data lines are shared between all SPI devices. So adding more external memories is straightforward by just using another SS pin from the MCU.

Initializing the Cortex-M3 SPI Peripheral

The Cortex-M3 SPI peripheral must be configured before it can communicate with the external SPI memory device. The following steps are typically required:

1. Enable the SPI peripheral clock in the MCU clock control registers.
2. Configure SPI pins for alternate function in the GPIO peripheral.
3. Set the SPI operating mode – choices include Motorola, TI, and National Semiconductor modes.
4. Configure clock polarity (CPOL) and phase (CPHA).
5. Select the SPI clock rate up to the maximum supported speed.
6. Choose the bit transfer order like MSB first or LSB first.
7. Set the word length from 4 bits to 16 bits as needed.
8. Enable SPI master mode of operation.
9. Initialize the slave select pin(s) connected to the memory chip(s).
10. Clear the SPI peripheral status flags and enable interrupts if needed.

The Cortex-M3 SPI registers control, status, data, and configuration registers are used to initialize the peripheral with the required communication settings. Once initialization is complete, the SPI peripheral can communicate with the external SPI memory device.

Reading and Writing SPI Memory

With the Cortex-M3 SPI peripheral initialized, communicating with the external SPI memory uses the data register, status flags, and control registers. Some common SPI memory operations include:

• Single Read – Set slave select, write SPI read instruction, read data byte/word.
• Sequential Reads – Set slave select, write read instruction with address, read data stream.
• Page Read – Set slave select, write instruction for page read, read data bytes.
• Single Write – Set slave select, write SPI write instruction, write data byte/word.
• Sequential Writes – Set slave select, write instruction with address, write data stream.
• Page Write – Set slave select, write page program instruction, write data bytes.
• Full Erase – Set slave select, send write enable, send sector or chip erase instruction.

The SPI status register and interrupt flags are used to detect communication errors and track progress. Data is loaded into the SPI data register and shifts out MOSI or shifts in from MISO automatically based on the configuration. The SPI peripheral handles the interface protocol details.

Using SPI Memory for Data Storage

External SPI memory can be used for general data storage needs with a Cortex-M3 microcontroller. The memory appears as a sequence of readable and writeable bytes or words. The Cortex-M3 software can perform address calculations to access specific memory locations.

Data can be read and written directly using SPI memory read and write instructions. Or with some additional firmware, the external memory can look like a full file system for storing application data objects, logs, multimedia files, etc. The capacity depends on the memory size – ranging from kilobytes for smaller chips to megabytes for larger memories.

The advantage of SPI memory for data storage is that it persists even when power is removed from the Cortex-M3 microcontroller. The memory provides non-volatile storage unlike RAM, and data can be accessed synchronously at high speed unlike external flash drives.

Using SPI Memory for Code Storage

With additional configuration, external SPI memory can also be used to hold code for the Cortex-M3 processor to execute. This allows the memory to store larger and more complex firmware programs beyond what internal flash memory can hold. The process involves:

1. Configure external memory regions in the Cortex-M3 memory map registers.
2. Set up the linker script to place executable code sections into external memory.
3. Initialize the external memory interface and generate clocks.
4. Copy code sections from flash into external memory at startup.
5. Configure the Cortex-M3 vector table to use the external memory.

This allows the processor to start fetching and executing instructions from external SPI memory. High speed access provides good performance. The program code size is only limited by the external memory capacity. With full access to both code and data, an SPI memory chip looks like an extension of the Cortex-M3’s own internal memories.

Example Code for Accessing SPI Memory

Here is example C code for reading and writing an external SPI flash memory connected to a Cortex-M3 processor. The MemoryData structure defines fields matching the SPI flash registers: struct MemoryData { uint8_t Instruction; uint32_t Address; uint8_t HighByte; uint8_t LowByte; };

A read function passes a memory address and returns the byte read: uint8_t SPIFlash_ReadByte(uint32_t Address) { // Initialize struct with Read instruction and address MemoryData.Instruction = READ; MemoryData.Address = Address; // Set slave select low to start transaction SS_LOW(); // Send read instruction and address SPI_SendStruct(MemoryData); // Read data byte MemoryData.HighByte = SPI_ReceiveByte(); // Set slave select high to end transaction SS_HIGH(); // Return read data return MemoryData.HighByte; }

A write function accepts a byte value to be written to a given address: void SPIFlash_WriteByte(uint32_t Address, uint8_t Data) { // Initialize struct with Write instruction and address MemoryData.Instruction = WRITE; MemoryData.Address = Address; MemoryData.HighByte = Data; // Set slave select low to start transaction SS_LOW(); // Send write instruction, address, and data SPI_SendStruct(MemoryData); // Set slave select high to end transaction SS_HIGH(); }

The SPI peripheral and slave select pins handle the transfer details. The code initializes the command struct, sends it over SPI, then reads or writes the data byte. The external SPI flash memory provides simple sequential or random access storage.

Conclusion

Connecting external SPI memory enhances a Cortex-M3 microcontroller with additional storage capacity for data and code. With the SPI peripheral handling the interface, the memory appears as a directly accessible array of bytes or words to the software. Configuration options support using the external memory for bulk data storage or executing larger programs.

With large SPI memories available, external memory can significantly extend the storage capabilities of a Cortex-M3 system. The fast synchronous interface provides good performance, similar to accessing the internal memory of the microcontroller. And the simple SPI interface makes it easy to add more memory as needed through all the SPI pins brought out on most Cortex-M3 devices.