The Cortex-M85 is an ARM processor targeted for advanced driver assistance systems (ADAS), autonomous driving systems, industrial and IoT applications. It has configurable on-chip memory to meet different application needs.
On-Chip Memory Configuration
The Cortex-M85 allows flexible configuration of on-chip memories including:
- Up to 2MB of tightly coupled memory (TCM)
- Up to 8MB of low latency RAM (LLRAM)
- Up to 64KB of read only memory (ROM)
The total on-chip memory size can be up to 10MB depending on configuration. Let’s look at each of these memory types in more detail:
Tightly Coupled Memory (TCM)
The Cortex-M85 has up to 2MB of TCM, which is fast on-chip RAM tightly integrated with the CPU for low latency access. It is split into separate instruction TCM (ITCM) and data TCM (DTCM) regions. Each TCM region can be configured from 32KB to 1MB in size.
TCM provides single cycle access latency, which is critical for real-time applications. It acts as a cache and buffer for frequently used code and data to reduce accesses to slower off-chip memory.
Low Latency RAM (LLRAM)
LLRAM provides up to 8MB of on-chip memory with access latency of 2-3 cycles. It has higher density than TCM while still providing fast access for real-time tasks.
LLRAM is configurable from 128KB to 8MB and can be used for multiple purposes:
- Data RAM for stack, global and static data
- Instruction RAM for application code
- Direct Memory Access (DMA) for peripherals
- Frame buffer for video/graphics data
LLRAM provides flexibility to optimize the memory system for different applications.
Read Only Memory (ROM)
The Cortex-M85 includes up to 64KB of on-chip ROM to store boot code and critical algorithms. ROM enables execution from a known good code base immutable to tampering or corruption.
The ROM size is configurable from 0KB to 64KB. It is ideal for booting and security critical functions such as:
- Bootloader
- Secure vault
- Cryptographic algorithms
- Fault recovery routines
Optimizing On-Chip Memory Configuration
The optimal on-chip memory configuration depends on the application requirements. Some key considerations include:
- Real-time performance – TCM provides the lowest latency and highest guaranteed performance for real-time tasks.
- Code size – ITCM capacity limits code size that can execute with single cycle latency.
- Data storage – DTCM and LLRAM capacity for stack, heap, globals etc.
- Buffering – TCM and LLRAM for hardware peripherals buffers and frame buffers.
- Security – ROM for secure code regions and cryptographic data.
- Boot time – ROM accelerates boot time by executing code directly from reset.
For example, an ADAS system may allocate:
- 1MB ITCM – For critical perception algorithms
- 1MB DTCM – For algorithm data
- 6MB LLRAM – For frame buffering and general data
- 64KB ROM – For bootloader and secure functions
This provides real-time response for algorithms, low latency memory for hardware buffers, and hardware enforced boot protection.
An IoT application may have a different optimal configuration tailored for its usage.
The Cortex-M85 memory architecture is highly flexible to balance performance, cost and security for a wide range of embedded applications.
External Memory Interface
In addition to internal memory, the Cortex-M85 includes a memory interface to connect to external memories. This allows much larger memory capacity to complement the on-chip memory.
The external memory interface includes:
- AXI 64-bit bus for high bandwidth external memory access
- Up to 16 TeraBytes physical address space
- ECC support for high reliability memory protection
- Up to 1600MT/s data rate
External memories commonly connected via the interface include:
- DDR DRAM – For large data storage capacity
- DDR PSRAM – For memory mapped IO buffers
- Quad-SPI flash – For boot code and non-volatile storage
- HyperBus Memory – For low latency external memory
The Cortex-M85 memory architecture provides great flexibility to meet demanding memory requirements with its configurable on-chip memory and high bandwidth external memory interface.
Memory Protection Unit
The Cortex-M85 includes an integrated Memory Protection Unit (MPU) to enforce hardware level memory protection. This is especially important for safety critical applications.
The MPU provides the ability to:
- Divide memory into up to 16 regions
- Configure each region access permissions
- Enable/disable region overlap checking
- Set region matching attributes e.g. user mode access
Example uses of the MPU include:
- Protecting on-chip memories for secure code and data storage
- Creating privileged execution regions for trusted code
- Enforcing memory boundaries between RTOS tasks
- Hardening external DDR memory against exploits
The MPU ensures even buggy or malicious code cannot corrupt critical on-chip code and data structures by restricting memory accesses.
In Summary
The Cortex-M85 includes a flexible on-chip memory architecture with:
- Up to 2MB TCM for real-time low latency access
- Up to 8MB LLRAM for data storage and buffering
- Up to 64KB ROM for secure boot functions
The total on-chip memory size can be configured up to 10MB to meet application requirements.
An external memory interface allows connecting to large external memories like DRAM, SRAM and flash.
The integrated MPU enables creating protected memory regions for security critical code and data.
Overall the Cortex-M85 memory system provides an excellent combination of real-time performance, flexibility and security for advanced embedded applications.
