The Cortex-M0 is an ARM processor core designed for microcontroller applications. It is an extremely small and low power core aimed at devices with limited memory and processing requirements. The Cortex-M0 has a very modest amount of memory compared to higher-end Cortex-M cores.
The Cortex-M0 processor itself does not contain any on-chip memory. Instead, it is designed to interface with external memories and peripherals. The amount of memory present in a Cortex-M0 system depends on the specific microcontroller or system-on-chip (SoC) implementation.
Microcontroller manufacturers who license the Cortex-M0 core can choose to integrate memories and peripherals together with the core in an SoC. It is up to them to decide how much flash memory, RAM, and ROM to include based on the target application and price point.
That said, given its focus on low-cost and memory constrained applications, Cortex-M0 chips generally have modest memory capacities. A typical configuration would include:
- 32-128 KB of flash memory for storing code and data
- 4-16 KB of SRAM for volatile data storage
- Optional ROM or EEPROM for bootloader or configuration data
For example, the STM32F030x4/x6 series of microcontrollers based on the Cortex-M0 core contains 32-64 KB flash and 4-8 KB SRAM. NXP’s LPC800 family includesflash ranging from 16-64 KB and SRAM ranging from 4-20 KB.
The modest integrated memory sizes can be expanded by interfacing external memory chips. The Cortex-M0 supports external memories through its External Memory Interface (EMI), which includes address and data buses that can be connected to additional memories.
Using the EMI, a Cortex-M0 microcontroller could be connected to external memories including:
- NOR and NAND flash for higher capacity code storage
- SRAM for faster data storage
- PSRAM for pseudo static RAM
- DRAM for dynamic memory
The exact memory configuration depends on the requirements of the application. For example, a wireless sensor node may require hundreds of kilobytes of flash storage for over-the-air firmware updates. A motor controller may need faster external SRAM for real-time control algorithms.
Memory Protection Unit
The Cortex-M0 contains a Memory Protection Unit (MPU) which allows assigning access permissions to blocks of memory. The MPU improves reliability and security by preventing invalid memory accesses that could crash the system or expose private data.
The Cortex-M0 MPU supports:
- Up to 8 memory regions
- Configurable read, write, and execute permissions per region
- Overlap protection for regions
- Locking down regions to prevent further changes
The MPU is commonly used to create a privileged execution region for the OS kernel distinct from the application space. This prevents buggy application code from accidentally corrupting the kernel.
The Cortex-M0 has a standardized memory map which separates flash, RAM, peripherals, and external memory regions into fixed address ranges.
At the bottom of the 4GB address space is the 16MB system memory region for on-chip memories like flash and SRAM. This is followed by 256MB of external memory mapped via the EMI interface.
The next 512MB are reserved for various system peripherals. At the top of the address space is a 3GB region for vendor specific peripheral customization and expansion.
This standardized memory layout makes it easier to reuse code across different Cortex-M0 chips. The hardware abstraction layer in the ARM CMSIS libraries exploits this known memory mapping.
Flash Patch and Breakpoint Unit
The Cortex-M0 contains a Flash Patch and Breakpoint (FPB) unit to support in-field firmware updates and debugging.
The FPB unit can redirect instruction fetches from flash to RAM. This allows patching flash content at runtime which is useful for:
- Applying firmware updates
- Workaround for chip errata
- Runtime tuning of algorithms
The FPB also provides 2 hardware breakpoints for debugging. When fetching an instruction from a breakpoint address, the Cortex-M0 will enter debug state rather than executing the instruction. This causes it to halt and attach a debugger.
For debugging and programming, the Cortex-M0 supports ARM CoreSight debug components including:
- Embedded Trace Macrocell (ETM) – instruction trace
- Instrumentation Trace Macrocell (ITM) – printf style debugging
- Debug Access Port (DAP) – debugger interface
These debug modules are optional components that chip vendors can choose to integrate. They allow advanced real-time debugging and performance profiling capabilities.
The Cortex-M0 is designed for low-power operation rather than peak performance. It has a simple 2-stage pipeline without any instruction parallelism or caching. All memory accesses are single cycle.
The lack of a memory cache combined with the slow clock speeds of Cortex-M0 chips results in memory access times on the order of 100s of clock cycles. This level of performance is adequate for simple embedded applications.
For example, with a typical 48 MHz clock speed, flash and RAM access times would be in the 10s of microseconds. Slower external memories would see correspondingly slower access times. In applications with demanding memory bandwidth requirements, developers may need to optimize code for fewer accesses.
To conserve power consumption, the Cortex-M0 supports multiple low power sleep modes that turn off the core but retain memory state. The supported sleep modes include:
- Sleep – CPU stopped, peripherals and memories retain state
- Deep sleep – Most clocks gated off, only low power circuits active
- Standby – SRAM powered off, only wakeup logic active
- Shutdown – All power removed except wakeup logic
Transitioning between run and sleep modes allows optimizing for the lowest power consumption while still meeting real-time requirements. The Cortex-M0 memory system is designed to preserve state across these transitions.
While the Cortex-M0 integrated memory sizes are modest, its flexible bus architecture allows connecting to almost any external memory. With external memories, the practical limit comes down to board space, power budgets, and memory addressing range.
Upgrading an existing design from a smaller Cortex-M0 chip to a larger capacity one is also generally straightforward. The compatible memory map and peripherals simplify reuse of software across different microcontroller variants.
In summary, the Cortex-M0 is highly configurable when it comes to memory capacity. Integrated memory sizes are usually modest, ranging from kilobytes up to around 100KB. But total system memory can be expanded through the addition of external memories. The Cortex-M0 MPU and debug features help make effective use of the limited capacity while supporting upgrades.