The Cortex-M1 is an ARM processor core designed for microcontroller applications. It was one of the first Cortex-M series cores developed by ARM and was introduced in 2004. The Cortex-M1 is a 32-bit RISC processor optimized for low power consumption and features a 3-stage pipeline, Von Neumann architecture, and integrated Memory Protection Unit (MPU).
One of the key specifications of any microcontroller or processor is the amount of memory it has, both for storing instructions/code and for storing data during operation. The total memory size and layout is an important factor in determining the performance and capabilities of a processor like the Cortex-M1.
The Cortex-M1 supports up to 1MB of program memory for storing code and instructions. This memory is typically implemented as on-chip flash memory or off-chip NOR flash. The exact amount of program memory implemented can vary between different microcontroller products utilizing the Cortex-M1 core. Many devices have between 32KB and 128KB of program flash available.
The program memory is accessed via a Von Neumann architecture on the Cortex-M1. This means that both code and data share the same unified memory space rather than having separate address spaces. Program memory is read-only and is used to store executable code. It cannot be written to at runtime.
In addition to flash memory for program storage, the Cortex-M1 also contains SRAM memory for storing data like variables, stack, and heap at runtime. The amount of SRAM can range from 4KB up to 64KB on different microcontroller implementations.
The SRAM provides fast read/write access for volatile data storage during program execution. It can be accessed directly by the Cortex-M1 core without having to program flash memory. The SRAM size puts a limit on the amount of runtime data a program can utilize before running out of memory.
Breakdown of SRAM Memory
The total SRAM memory space on a Cortex-M1 device is further broken down into different sections:
- Heap: Used for dynamic memory allocation using malloc/free. The heap grows up from the top of the SRAM memory space.
- Stack: Used by functions to store local variables and pass parameters. The stack grows down from the top of SRAM.
- Global/Static Variables: Storage for global and static variables in code.
- Vector Table: A table of exception/interrupt handlers. Occupies the bottom 256 bytes of SRAM.
The remaining free SRAM between the heap, stack, and static variables can be used as general purpose memory if needed by a program.
External Memory Interface
In addition to on-chip program flash and SRAM memory, the Cortex-M1 supports adding additional external memory through its External Memory Interface (EMI). This allows SRAM, flash, or devices like an SDRAM chip to be connected to the microcontroller via an external bus.
Using the EMI, total memory capacity can be greatly increased compared to just the on-chip memory alone. For example, up to 64MB of external flash memory can be added. The external memory is mapped into the Cortex-M1’s memory space and is accessed just like internal SRAM/flash.
The EMI operates at half the CPU frequency, so with a 60 MHz Cortex-M1 core, the EMI bus could run at 30 MHz. Multiplexed address/data lines are used to reduce pin count. Wait states can be inserted to accommodate slower external memories.
Memory Protection Unit
The Cortex-M1 contains an integrated Memory Protection Unit or MPU. This allows control over memory access permissions in different regions of the address space, improving reliability and security.
For both program flash and SRAM memory, the MPU can set read, write, and execute permissions on up to 8 different memory regions. This can prevent corruption of code and data by restricting access to only authorized areas.
Cortex-M1 Memory Map
To summarize, the total memory map on a typical Cortex-M1 configuration looks like:
- Up to 1 MB Program Flash (code memory)
- Up to 64 KB SRAM (data memory)
- Heap (top)
- Stack (grows down from top)
- Global Variables
- Vector Table (bottom 256 bytes)
- Up to 64 MB External Memory via EMI
The Cortex-M1 memory architecture with different SRAM regions and optional external memory provides flexible memory configurations suitable for a wide range of embedded applications. The total memory size is ultimately dependent on the specific microcontroller implementation by the silicon vendor.
Cortex-M1 Memory Performance
In terms of memory access performance, the Cortex-M1 can fetch up to two instructions per clock cycle from program memory thanks to its dual-issue pipeline. Single cycle SRAM accesses minimize data access latency. External memory interfaces operate at half CPU frequency but include wait state support.
Overall, the Cortex-M1 memory subsystem provides low latency access and good performance despite the limited size and simplicity common of microcontroller systems. Fetching and reading/writing data from program, SRAM, and external memories can happen efficiently relative to the CPU speed.
In most cases, the Cortex-M1 memory size and bandwidth is more than sufficient for common microcontroller applications which need to run at lower frequencies and fit in smaller memory footprints. Performance is optimized for reduced power rather than maximum speed.
In summary, the exact memory capacity of the Cortex-M1 depends on the specific microcontroller implementation. But the core supports up to:
- 1MB of on-chip program flash memory
- Up to 64KB of SRAM for data
- Up to 64MB of external memory via the EMI
Memory access performance is optimized for low power embedded systems with dual issue instruction fetching, single cycle SRAM, and half frequency external memory interfaces. The Cortex-M1 memory architecture balances size, bandwidth, and power for typical microcontroller applications.