The Cortex-M0+ is an ultra low power 32-bit ARM Cortex-M microcontroller core produced by ARM Holdings. It has a simplified design compared to higher-end Cortex-M cores, optimized for low cost and low power embedded applications. The Cortex-M0+ core itself does not contain any memory, rather it interfaces with on-chip memory provided by the silicon manufacturer integrating the core.
The amount of memory integrated with a Cortex-M0+ implementation can vary greatly depending on the target application. But in general, Cortex-M0+ microcontrollers tend to have a small memory footprint, ranging from 16KB to 256KB of flash memory for code storage, and 4KB to 64KB of SRAM for data storage. Larger memory sizes are possible, but less common for M0+ devices aimed at ultra low power operation.
Flash Memory
The flash memory on a Cortex-M0+ microcontroller stores the executable program code. It is non-volatile memory, meaning it retains its contents even when power is removed from the chip. Flash memory capacities for Cortex-M0+ MCUs typically range from:
- 16KB to 32KB – Small footprint MCUs aimed at simple sensing and control applications
- 64KB to 128KB – General purpose MCUs suitable for a wide range of low power applications
- 256KB – Larger MCUs that require more code space
Some examples of Cortex-M0+ flash memory sizes from major manufacturers include:
- STM32L011K4 – 16KB flash
- NXP LPC812M101 – 32KB flash
- TI MSP430FR2101 – 64KB flash
- Microchip SAM L10 – 128KB flash
- Nordic nRF51822 – 256KB flash
Factors that influence flash memory size include the target application code size, need for over-the-air (OTA) firmware updates, and cost. More complex applications require storing more lines of code, while OTA update capability mandates keeping a portion of flash available at all times. Larger memory sizes increase silicon die area and cost.
SRAM Memory
The SRAM on a Cortex-M0+ microcontroller stores writable data used during program execution. It is volatile memory, meaning its contents are lost when power is removed. SRAM capacities for Cortex-M0+ MCUs typically range from:
- 4KB to 8KB – Small footprint MCUs aimed at cost sensitive applications
- 16KB to 32KB – General purpose MCUs suitable for a wide range of low power applications
- 64KB – Larger MCUs that require more data memory
Some examples of Cortex-M0+ SRAM sizes include:
- NXP LPC800 – 4KB SRAM
- STM32L010x4 – 8KB SRAM
- Microchip SAMD20 – 16KB SRAM
- Renesas RL78 – 32KB SRAM
- Cypress PSoC 4000S – 64KB SRAM
Factors influencing SRAM size include the need to buffer real-time data, store intermediate results during calculations, hold program variables and stacks, and retain memory during low power modes. More SRAM provides programming flexibility at the expense of increased silicon area and cost.
ROM Memory
In addition to flash and SRAM, some Cortex-M0+ microcontrollers include read-only memory (ROM) to store constant system data. ROM memory is non-volatile and hardcoded during chip manufacturing. Typical ROM sizes are 4KB to 32KB, and may store bootloader code, firmware libraries, or factory calibration data.
Memory Mapping
The Cortex-M0+ uses a single flat, linear memory map to access its memory regions. Flash, SRAM, and ROM are mapped into a single contiguous address space, maximizing flexibility for the programmer. There are no memory segmentation limitations with this approach. The processor’s memory protection unit (MPU) can be used to partition and secure memory if needed.
Expansion Options
While Cortex-M0+ MCUs have modest onboard memory sizes, there are ways to expand storage capacity if needed:
- External Flash – External serial flash ICs can be added via the processor’s SPI peripheral to provide megabytes of additional non-volatile storage.
- External RAM – Supplementary external RAM chips can be interfaced using FSMC, octal SPI, or parallel bus to give more temporary data storage.
- SD Card – Secure Digital (SD) card interfaces allow gigabytes of removable storage via the SD card slot.
However, all these options come at the cost of increased board space, power demands, and system complexity. The small integrated memory sizes are part of what makes Cortex-M0+ MCUs suited for low-power and space-constrained applications. For projects needing more storage, a Cortex-M3 or Cortex-M4 may be a better solution.
Memory Access Times
The Cortex-M0+ is able to access on-chip flash and SRAM memory very efficiently, typically in a single cycle. This provides deterministic timing for instruction fetches and data loads/stores. Actual access times depend on the silicon process used. Some examples include:
- 16nm FinFET – 1 cycle (0.25 ns @ 4 GHz CPU clock)
- 40nm CMOS – 1 cycle (2.5 ns @ 400 MHz CPU clock)
- 90nm CMOS – 1 cycle (11 ns @ 90 MHz CPU clock)
In addition to raw access time, the Cortex-M0+ 3-stage pipeline means the processor can perform a memory access every clock cycle. This keeps the pipeline filled and maximizes memory bandwidth, even when running at very high frequencies.
Memory Bandwidth
The combination of fast access times and an efficient pipeline gives Cortex-M0+ cores very good memory bandwidth despite their limited resources. For example, a Cortex-M0+ accessing 16-bit values from 90 nm SRAM at 90 MHz can achieve:
- Peak bandwidth = 90 MHz * 2 bytes per access = 180 MB/s
- Sustained bandwidth ~90% of peak = 160 MB/s
This is ample for many embedded applications. More advanced memory architectures like multi-bank SRAMs can sustain maximum bandwidths. External memory bandwidth is dependent on interface protocol – SPI at 20 MHz may give 20 MB/s, while FSMC at 60 MHz could reach 480 MB/s.
Memory Controllers
The Cortex-M0+ core relies on integrated memory controllers provided by the silicon manufacturer to interface with on-chip memories. These include:
- Flash Controller – Manages flash memory access and programming operations.
- SRAM Controller – Controls SRAM read/write timing and interface signaling.
- ROM Controller – Handles access to read-only data stored in ROM.
The controllers handle all timing, bus arbitration, error correction, redundancy, and other aspects governing memory access. Having dedicated controllers improves performance and reduces the load on the CPU core. The Cortex-M0+ design relies on the silicon vendor to customize the controllers for their manufacturing process and memory architecture.
Memory Protection Unit
The Cortex-M0+ contains an optional memory protection unit (MPU) to guard and partition memory. The MPU allows creating secure regions for privileged code and data storage. Access permissions, cache settings, execution rights, and other protections can be configured per-region under software control. This prevents corruption of critical code and data at runtime.
Instruction and Data Caches
To maximize performance, some Cortex-M0+ microcontrollers utilize small instruction and data caches. These small fast memories store frequently used code and data closer to the core to reduce external memory accesses. Typical cache sizes are just 4KB to 16KB, keeping area impact low. Caches improve average access times and increase average bandwidth of external memories. Effective caching relies on the silicon vendor properly tuning cache policy settings for optimal hit rates.
Write Buffers
Many Cortex-M0+ microcontrollers employ write buffers to accelerate storing data to flash memory. Write buffers allow the CPU to issue multiple flash write commands in quick succession, rather than waiting for each program operation to complete. The hardware buffer collects data to be written and releases the CPU core, improving write throughput. Buffers are typically 128 to 512 bytes in size – enough to capture a burst of writes without overflowing.
Conclusion
In summary, the Cortex-M0+ memory subsystem balances performance against extreme size and power efficiency. The core itself does not contain memory, it leverages on-chip flash, SRAM, and ROM provided by the manufacturer. Typical memory sizes range from just kilobytes up to a maximum of ~256KB flash and ~64KB SRAM. The limited resources reflect the intended ultra low power applications. External memories can provide more capacity when needed. Integrated memory controllers and caches aim to maximize bandwidth despite the constraints. The end result provides impressive capability from a very compact low power microarchitecture.
