How many interrupts does the arm cortex-M0 contain?

The ARM Cortex-M0 is an ultra low power 32-bit RISC processor core designed for microcontroller applications. It is the smallest and simplest member of the Cortex-M processor family, aimed at replacing 8-bit and 16-bit microcontrollers in cost sensitive and power constrained embedded systems.

The Cortex-M0 core contains a single interrupt controller called the Nested Vectored Interrupt Controller (NVIC). The NVIC supports up to 32 external interrupt sources, allowing it to handle interrupts from various on-chip peripherals and external interrupt sources.

NVIC Interrupt Sources

The 32 interrupt sources supported by the Cortex-M0 NVIC are:

• 16 system exceptions (internal processor exceptions)
• Up to 16 external interrupts

System Exceptions

The 16 system exceptions supported by the NVIC are:

• Reset
• Non maskable interrupt (NMI)
• Hard fault
• Memory management fault
• Bus fault
• Usage fault
• Secure fault (only in Secure state)
• Supervisor call (SVCall)
• Debug monitor
• Pendable request for system service (PendSV)
• System tick timer (SysTick)
• Interrupt 0 (IRQ0) – Reserved
• Interrupt 1 (IRQ1) – Reserved
• Interrupt 2 (IRQ2) – Reserved
• Interrupt 3 (IRQ3) – Reserved
• Interrupt 4 (IRQ4) – Reserved

These system exceptions are generated by events internal to the processor, like reset,supervisor calls, processor faults, debugger access, etc. They have fixed interrupt numbers and priority levels configured by the ARM architecture.

External Interrupts

Up to 16 external interrupts (IRQ5 to IRQ20) can be handled by the NVIC. These interrupts are generated by events outside the processor, like peripherals, external interrupt sources, etc. The interrupt numbers, priority levels and routing of these external interrupts is flexible and can be configured by the user.

For example, on a microcontroller these external interrupts may be connected to on-chip peripherals like timers, ADC, external communication interfaces like SPI, I2C,etc. The interrupt controller allows assigning a unique interrupt number and priority level to each of these peripheral interrupts.

NVIC Features

Some of the key features of the Cortex-M0 NVIC are:

• Each interrupt source can be individually enabled/disabled
• Configurable priority levels – Each interrupt can be assigned one of 16 priority levels
• Level and pulse detection of interrupt signals
• Wakeup from sleep/low power modes on interrupt
• Processor state automatically saved on interrupt entry and restored on return
• Stacking to allow nesting of interrupts
• Efficient exception handling without software intervention

These features make interrupt handling seamless and efficient on the Cortex-M0 processor.

Interrupt Handling Process

Here is a quick summary of how the NVIC handles interrupts on the Cortex-M0:

1. An interrupt event, like a peripheral interrupt or system exception, triggers an interrupt request to the NVIC.
2. NVIC checks if the interrupt is enabled and asserts the interrupt signal to the processor core.
3. The core finishes executing the current instruction, saves its state and transfers control to the NVIC.
4. NVIC determines the interrupt number and looks up the corresponding interrupt service routine (ISR) address in the Vector Table.
5. NVIC sets the core stack pointer to the interrupt stack.
6. The first instruction of the ISR is executed.
7. On ISR completion, the stack and core state is restored and execution resumes from the original point.

This automated interrupt handling reduces interrupt latency and simplifies software development.

Configuring Interrupts

The NVIC interrupt behavior can be configured using registers provided as part of the System Control Block (SCB). This includes:

• Setting interrupt enables/masks
• Setting interrupt priority levels
• Setting the ISR addresses in the vector table
• Setting the stack pointers
• Enabling specific system exceptions
• Configuring power control, wakeups, etc.

This gives developers complete flexibility to tailor the NVIC as per their application requirements.

Benefits of Cortex-M0 NVIC

Some key benefits of the Cortex-M0 interrupt architecture are:

• Low latency interrupt handling
• Reduced software overhead
• Flexible prioritization of interrupts
• Nested interrupts for real-time response
• Wakeup from sleep on interrupts
• Simplified integration of multiple peripherals
• Reliable and deterministic interrupt handling

These capabilities allow developers to easily integrate multiple real-time tasks, peripherals and communication interfaces in their Cortex-M0 designs.

Use Cases

The Cortex-M0 NVIC makes it well suited for various low power, real-time embedded applications like:

• IoT edge nodes
• Industrial sensors and controllers
• Home automation
• Consumer electronics
• Wearable devices
• Medical devices
• Automotive body control modules

Interrupt handling is a key requirement in such embedded applications. The Cortex-M0 NVIC enables robust, low-latency interrupt handling crucial for these use cases.

Summary

In summary:

• The Cortex-M0 NVIC supports 32 interrupt sources – 16 fixed system exceptions and up to 16 configurable external interrupts.
• It provides automated, low overhead interrupt handling with flexible prioritization and minimum software intervention.
• The NVIC is highly configurable to address various application needs.
• Reliable, low latency interrupt handling enables integrating multiple real-time tasks in Cortex-M0 designs.
• The Cortex-M0 interrupt architecture is ideal for interrupt-driven embedded applications like IoT, industrial, consumer and medical devices.