The number of available interrupts in ARM Cortex-M3 and Cortex-M4 microcontrollers depends on the specific chip implementation. However, the Cortex-M3 and Cortex-M4 architectures themselves allow for a substantial number of flexible interrupts to support a wide range of applications.
In general, the Cortex-M3 and Cortex-M4 microcontrollers have several interrupt sources available to them, including:
- External interrupts
- Internal interrupts
- Software interrupts
The exact number of interrupts available varies by microcontroller model, but there are typically around 30-60 potential interrupt sources in total. Let’s take a closer look at the different categories of interrupts in more detail:
External interrupts allow the processor to respond to signals from external hardware components. For example, external interrupts can come from sources like external sensors, buttons/switches, or communication interfaces.
The Cortex-M3 and M4 provide extensive flexibility for handling external interrupts. There are typically 8-16 dedicated external interrupt lines available. Each line can be individually configured to be level or edge triggered, so developers have control over precisely when an interrupt is triggered.
External interrupt lines often support multiple priority levels as well. Higher priority interrupts can preempt lower priority interrupts, allowing more time-critical events to be serviced faster. Priorities are configurable, giving developers control over the relative importance of different external events.
Overall, the plentiful external interrupts with priority and edge/level controls allow Cortex-M3/M4 microcontrollers to smoothly interface with diverse sets of external peripherals and respond appropriately when external events occur.
Aside from external hardware, Cortex-M3/M4 MCUs also generate internal interrupts from on-chip resources and software events. These can originate from internal timers, communication peripherals, comparators, ADCs, DMA controllers, and more.
For example, a timer module can generate an interrupt when it reaches a set count value. An ADC can generate an interrupt when a conversion is complete. And serial communication blocks can generate interrupts when transmission or reception buffers are full.
These types of internal interrupts allow the processor to efficiently synchronize with the state of on-chip resources without constantly polling status registers. The number of internal interrupt sources varies by microcontroller model, but generally there are 15-30+ different internal interrupt lines available.
As with external interrupts, internal interrupt sources can have configurable priorities to allow more time-sensitive events to preempt less critical ones when needed.
Lastly, Cortex-M3 and M4 MCUs provide support for software generated interrupts. These allow interrupts to be triggered directly by software for specialized use cases.
For example, an operating system (OS) may use software interrupts for task switching. When the currently running task needs to be suspended, the OS would trigger a software interrupt which causes a context switch to the next scheduled task.
Software interrupts are also useful for emulating hardware interrupts when prototyping. An engineer can manually trigger software interrupts while debugging to simulate real external events before the actual hardware is ready.
There are typically 2-4 software generated interrupt lines available in Cortex-M3/M4 microcontrollers. As with hardware interrupts, software interrupts can also have programmable priorities.
Interrupt Priority Levels
A key feature of the Cortex-M3 and M4 interrupt architectures is support for multiple priority levels. Each interrupt source can be assigned a priority from 0 (highest) to 255 (lowest).
When multiple interrupt requests are pending simultaneously, the MCU will service the highest priority one first. Lower priority sources will remain pending until no higher priority interrupts are active.
Being able to assign priorities allows developers to design interrupt service routines (ISRs) tailored to their application requirements. For example, extremely latency-sensitive interrupts like an emergency stop button could be set to priority 0. While less critical interrupts like a low buffer watermark indicator might have a lower priority level.
Setting appropriate priorities is an important part of ensuring that key application events are serviced deterministically. The Cortex-M3 and M4 give developers significant control over this through configurable, multi-level priorities for both internal and external interrupt sources.
Interrupt Vector Table
The Cortex-M3 and M4 processors organize active interrupt requests in a structured way using the Interrupt Vector Table (IVT). This is a lookup table that the processor references when an interrupt occurs.
Each entry in the IVT corresponds to a specific interrupt source. The entry contains the memory address of the ISR that should execute when that particular interrupt is triggered.
So in summary, when an interrupt occurs:
- The processor suspends main program execution and jumps to the IVT
- It looks up the address of the ISR for the requested interrupt source
- The processor executes the ISR code pointed to by the vector table
This standardized vector table approach allows interrupts from any source to be handled in a clean, consistent way. The number of entries in the vector table directly corresponds to the number of available distinct interrupts in the microcontroller.
Typical Interrupt Counts
Now that we’ve covered the different types of interrupts and how they are organized by the Cortex-M3/M4, let’s look at some example interrupt counts for specific microcontrollers:
- STM32F103xx Cortex-M3 MCUs: 60 total interrupts
- 16 external interrupts
- 23 internal peripheral interrupts
- 21 internal system interrupts
- STM32F407xx Cortex-M4 MCUs: 82 total interrupts
- 16 external interrupts
- 68 internal peripheral interrupts
- 2 software interrupts
- NXP LPC1769 Cortex-M3 MCU: 74 total interrupts
- 12 external interrupts
- 54 peripheral interrupts
- 8 software interrupts
As you can see, leading Cortex-M3 and M4 microcontrollers support 50-80+ distinct interrupts. The large number of flexible interrupt sources allows these MCUs to service events from a wide variety of internal and external sources.
Between the plentiful interrupts, configurable priorities, and standardized vector table structures, the Cortex-M3 and M4 interrupt architecture is designed to provide low-latency servicing of real-time, asynchronous events in embedded systems.
In summary, the Cortex-M3 and Cortex-M4 microcontrollers provide extensive interrupt capabilities through:
- Up to 16 external interrupt lines
- 15-68+ internal peripheral interrupts
- 2-8 software generated interrupts
- Total interrupts ranging from 50-82 across common MCU models
- Configurable interrupt priorities from 0 to 255
- Standardized vector table for consistent interrupt handling
The flexible, low-latency interrupt architecture allows Cortex-M3 and M4 processors to respond quickly to critical events while juggling numerous internal and external interfaces. The capabilities make these MCUs well suited for demanding embedded applications in industrial, automotive, consumer, and other segments.