Exceptions are events that disrupt the normal flow of instruction execution in a processor. They can be triggered by various conditions like illegal instructions, division by zero, memory access violations, interrupts etc. Handling exceptions properly is critical for robust and secure system operation. The ARM processors have a well-defined exception model to handle such events gracefully.
Overview of Exceptions in ARM
The ARM processors broadly classify exceptions into two types:
- Synchronous exceptions – These occur because of an instruction execution e.g. undefined instruction, conditional failed instruction etc.
- Asynchronous exceptions – These are unrelated to instruction execution and can occur at any time e.g. interrupts, resets etc.
When an exception occurs, the processor immediately stops normal instruction execution. It then starts exception handling by branching to a pre-defined vector address corresponding to the exception type. The vector table containing the exception vectors is located in a protected region of memory.
Key Components of ARM Exception Handling
Following are the key components involved in ARM exception handling:
ARM processors support following common types of exceptions:
- Reset – Assertion of reset signal
- Undefined instruction – Execution of invalid instruction opcode
- Software interrupt – Triggered by SWI instruction
- Prefetch abort – Instruction fetch from invalid memory
- Data abort – Load/Store from/to invalid memory
- IRQ/FIQ – Standard interrupt requests
Some ARM versions support additional exceptions types like fast interrupts (FIQs), vector catches, hypervisor calls etc.
Exception Vector Table
This table located in protected memory contains the entry point addresses for all supported exception types. When an exception occurs, the corresponding vector is looked up from this table and the control branches to the handler routine present at that address.
Some exceptions like Reset have higher priority than others. When multiple exceptions occur at the same time, the highest priority one gets handled first. Priority handling prevents preemption of critical exceptions by low priority ones.
Exception State Registers
These include the Exception Link Register (ELR) and Saved Program Status Register (SPSR) which store information about the state of the processor before exception entry. This data is used to resume normal operation after exception handling.
Exception Handling Process
Following steps are performed when an exception occurs in ARM:
- Pre-exception state saving – The processor automatically saves information like instruction address, register contents etc. to ELR and SPSR.
- Exception entry – Using the exception type, the corresponding vector is looked up from the vector table. The control is then transferred to the handler routine present at that address.
- Handler execution – The exception handler routine performs the required processing based on the exception type and system state.
- Exception return – The handler executes an exception return instruction to resume normal operation. This restores the pre-exception state using ELR and SPSR.
Thus ARM exceptions allow saving context, branching to specific handlers and resuming execution in an organized manner.
Unified Exception Handling
The ARMv6 architecture introduced a unified exception handling mechanism for all exception types using the same vector table. Earlier ARM versions had separate handling mechanisms for different exceptions.
Unified exception handling provides following benefits:
- Simpler overall design and implementation.
- Uniform handling procedure for all exceptions.
- Access to same set of registers by all exception handlers.
- Support for nesting exceptions.
Configurable Exception Handling
ARM processors provide a lot of flexibility and control in handling exceptions. Following configurable capabilities allow customizing exception handling:
- Selective enabling/disabling of exceptions – Individual exceptions can be enabled or masked based on requirements.
- Priority setting – Relative priorities for different exceptions can be configured.
- Custom trap handlers – Users can provide their own exception handler routines.
- Reserved trap handling – Trapping of undefined instructions can be configured.
- Vector table relocation – The exception vector table can be located as per memory requirements.
These capabilities allow ARM-based systems to handle exceptions in a very flexible manner.
Role of Operating System
The Operating System (OS) plays a key role in managing ARM exceptions. Typical OS responsibilities are:
- Initializing the vector table and handler addresses.
- Enabling/disabling exceptions as per system requirements.
- Handling critical exceptions like memory faults.
- Coordinating between application and low-level exception handling.
- Abstracting platform-specific details from applications.
- Providing mechanism for applications to handle exceptions cleanly.
The OS and applications complement each other to implement robust exception handling on ARM systems.
ARM processors provide built-in debugging support for analyzing exception handling. Important debugging features include:
- Debug registers – To configure exception triggering and handler entry.
- Monitor debugging mode – For low level debug access.
- JTAG/SWD interface – For system-wide debug access.
- Exception tracing – Recording exception related events.
These aid in debugging complex issues related to exceptions and their handling.
Efficient exception handling is critical for ARM processors. The well-defined exception models in ARM, involving prioritized exception types, precise state saving, configurable handling and OS coordination, enable robust system development. With comprehensive debugging support, ARM processors and their partners provide all the necessary ingredients for building fault-tolerant systems with graceful exception handling.