The STM32F1 series of microcontrollers based on the Cortex-M3 core from STMicroelectronics offer several boot modes and flexible memory mapping options. Understanding these boot modes and memory maps is key to leveraging the capabilities of these powerful chips.
STM32F1 Boot Modes
There are several boot modes available on STM32F1 devices to accommodate different application requirements:
Boot Mode 0 (System Memory Boot)
This is the default boot mode on power-up or reset. In this mode, the device boots from the embedded system memory. The system memory consists of flash memory and SRAM located inside the microcontroller itself. This provides a simple and self-contained boot solution.
Boot Mode 1 (System Memory Boot with DFU)
This mode is similar to Boot Mode 0, booting from internal system memory. However, it also enables Device Firmware Upgrade (DFU) capability over USB. This allows the flash memory to be re-programmed over USB with new firmware. The USB DFU implementation uses the USB DFU class specification.
Boot Mode 2 (Embedded SRAM Boot)
In this mode, the device boots directly from SRAM starting at address 0x00000000. This allows developers to download code into SRAM over JTAG/SWD and execute it. Booting from SRAM eliminates flash latency and can be useful for applications requiring low-latency startup like digital power conversion.
Boot Mode 3 (System Memory Boot via USART)
This mode boots from the internal system memory like Mode 0. However, it also initializes a USART peripheral to allow communication over a UART port. This enables serial wire debugging of code in flash memory and provides a simple printf/scanf capability.
Boot Mode 4 (Embedded SRAM Boot via USART)
A combination of Modes 2 and 3, this boots from SRAM to reduce latency but also initializes a USART for serial wire output. Useful for debugging code downloaded to SRAM.
Boot Mode 5 (Embedded ROM Boot)
This mode boots from the internal ROM embedded inside the Cortex-M3 core itself starting at 0x00000000. This ROM contains startup code and interrupt vectors, so it can be used to boot even without external flash or SRAM. Mainly useful as a safe startup mode.
Boot Mode 6 (System Memory Boot with IWDG)
Identical to Mode 0 but also initializes the Independent Watchdog Timer (IWDG). This allows the IWDG to reset the system if the firmware gets stuck and fails to periodically service the watchdog.
Boot Mode 7 (Boot from User Flash)
This boot mode allows booting from external flash memory connected to the FSMC/FMC interface. Useful for booting from larger external memories.
These boot modes provide flexibility to developers and enable different use cases. The boot mode is selected using the BOOT pins on the microcontroller.
STM32F1 Memory Mapping
The Cortex-M3 CPU uses a von Neumann architecture with a unified address space for both code and data. The STM32F1 memory map places different memories and peripherals at specific addresses in this unified 32-bit address space:
0x00000000 – 0x1FFFFFFF: Code Area (Up to 2GB)
This region is used for program code. It can accommodate up to 2GB of flash or ROM. The actual physical memories mapped here include:
- Internal FLASH memory (up to 512KB)
- External memory on FSMC/FMC (up to 2GB)
- Embedded ROM (32KB)
0x20000000 – 0x3FFFFFFF: SRAM Area (Up to 2GB)
This region is used for SRAM data. It can accommodate up to 2GB of SRAM. The actual physical memories mapped here include:
- Internal SRAM (up to 64KB)
- External SRAM on FSMC/FMC (up to 2GB)
0x40000000 – 0x5FFFFFFF: Peripheral Area (512MB)
This region maps the memory-mapped peripherals on the STM32 device. This includes peripherals like GPIO, USART, SPI, I2C, timers, ADC, DAC, etc. Each peripheral has a defined base address and offset within this region.
0x60000000 – 0x9FFFFFFF: External Devices (Up to 1.5GB)
This large address space is unused by the Cortex-M3 core itself and left open for mapping external devices like external memory or peripherals.
0xA0000000 – 0xDFFFFFFF: External RAM (Up to 1GB)
Up to 1GB of external RAM can be mapped to this address range. It is typically used with external SDRAM chips.
0xE0000000 – 0xFFFFFFFF: Cortex-M3 Private Peripherals (512MB)
The final 512MB address space is reserved for the core peripherals integrated inside the Cortex-M3 core itself like the SysTick timer, NVIC, SCnSCB, etc.
This predefined memory map enables efficient use of the 4GB unified address space provided by the Cortex-M3 core in the STM32F1 series microcontrollers.
Leveraging STM32F1 Boot Modes and Memory Mapping
Understanding the boot modes and memory mapping capabilities of STM32F1 microcontrollers enables developers to make optimal use of these features for their application:
- The flexible boot modes allow easy development, debugging, and field upgrades.
- Large internal and external memories can be leveraged by mapping code and data appropriately.
- Peripherals have predefined addresses simplifying access and control.
- Unused address regions provide room for future expansion and enhancements.
In summary, the STM32F1 boot modes and memory mapping provide a robust, flexible, and scalable architecture for embedded systems developers to build upon. Matching application requirements to the boot modes and defining an optimal memory map are key steps in leveraging the STM32F1 capabilities.
With a comprehensive understanding of these microcontroller features, developers can fully utilize the performance, capabilities, and cost-effectiveness of the STM32F1 Cortex-M3 family for their unique application needs.