The Cortex-M1 processor from ARM is a popular choice for IoT and embedded devices. DesignStart is a free IP platform from ARM that allows developers to easily integrate Cortex-M1 into their custom SoC designs. While DesignStart simplifies integration, debugging these custom designs brings unique challenges. This article provides a guide to debugging DesignStart Cortex-M1 projects using DAPLink, a popular open-source solution.
Introduction to the Cortex-M1 Processor
The Cortex-M1 processor is a 32-bit RISC core optimized for deeply embedded applications. Key features include:
- High energy efficiency with dynamic power scaling
- Excellent real-time interrupt handling performance
- DSP instructions for signal processing tasks
- Memory Protection Unit (MPU) for security
- Tightly coupled memory for low latency access
These characteristics make the Cortex-M1 well-suited for IoT endpoint devices. Its efficiency enables years of battery-powered operation while still providing good performance. The MPU improves security by isolating trusted code and data. Interrupts and deterministic execution are critical in real-time control systems. DSP instructions accelerate processing of sensor data.
Introduction to the DesignStart Program
While the Cortex-M1 core delivers compelling capabilities, integrating a modern ARM processor into a custom SoC is challenging. Much of the difficulty lies in implementing the processor subsystem with caches, bus interfaces, peripherals, and debug components.
DesignStart addresses integration challenges by providing these elements as pre-verified reference designs. Partners like TSMC and GlobalFoundries manufacture the resulting SoCs. DesignStart provides Cortex-M1 reference designs for both older 180nm and modern 40nm manufacturing processes. Silicon proven integration reduces risk and speeds time-to-market.
Debug Challenges with DesignStart Projects
While DesignStart simplifies integration, debugging these SoCs raises difficulties not found when working with off-the-shelf microcontroller boards. Key debugging challenges include:
- Lack of built-in debug hardware like SWD ports
- Need to implement debug probes and logic externally
- More intricate bring-up process without initializing firmware
- Requirements for host tools to communicate with custom SoC
For hobbyists and smaller teams, implementing a comprehensive debug interface is generally not feasible. DAPLink provides an alternative by leveraging the ARM CoreSight debugging architecture present on Cortex-M cores like the M1. The debug host runs on a PC while DAPLink handles target communication.
Introduction to DAPLink
DAPLink is an open-source circuit and firmware project that enables debug connections to Cortex CPUs via USB. It utilizes the CoreSight Debug Access Port (DAP) built into ARM cores. Key capabilities include:
- USB connection to host computer
- DAPLink firmware runs on embedded MCU, acts as middleman
- Drag-and-drop programming flash memory
- Open source design, runs on low-cost boards
- Works with many ARM IDEs and tools
Many low-cost development boards leverage DAPLink, including those with NXP KL25Z, LPC11U35 and LPC4357 MCUs. Additionally, the cheap and minimal LPC11U35 board makes an ideal DAPLink interface for custom targets.
Connecting DAPLink to DesignStart Cortex-M1
Interfacing a target DesignStart Cortex-M1 SoC to a DAPLink debugger involves connecting the hardware debug pins between the two boards. These include the low pin count serial wire debug port (SWD) and other CoreSight signals. The steps are:
- Identify SWD and nRESET signals on the Cortex-M1 test chip
- Connect corresponding pins from the DAPLink LPC11U35 board
- Verify target board power and decoupling
- Check for shorts or incorrect pins
- Connect both boards to host PC via USB
Carefully planned pin headers and wiring is vital for reliable operation. Double checking connections and following DesignStart documentation avoids common errors. For robustness, use short direct pin headers or wiring without intermediate connectors.
Configuring DAPLink Firmware
Out of the box, the firmware on the DAPLink interface board must be configured to communicate with the target Cortex-M1 DesignStart SoC. The open-source firmware is customized by updating a configuration file with parameters for the target debug interface. Key steps are:
- Download the DAPLink firmware source and project
- Configure the target interface settings
- Build and flash updated firmware to DAPLink
- Initialize DAPLink web interface
Interface configuration options match those documented for CoreSight in the Cortex-M1 DesignStart user guide. With the firmware rebuilt, the DAPLink can recognize the target device when connected via SWD and JTAG.
Using pyOCD Host Tools with DAPLink
With the hardware and firmware configured, pyOCD open source Python tools communicate with the target Cortex-M1 through the DAPLink interface. pyOCD features:
- Pure Python, runs on Linux, MacOS, Windows
- Supports SWD, JTAG and CMSIS-DAP protocols
- Flash programming and verification
- Downloads binaries to RAM for debug
- Debugging via GDB and IDE integration
- Scriptable API for test automation
After installing pyOCD, the target device can be queried to verify connectivity. The SoC is then be programmed via the command line or pyOCD’s gdbserver integration. Finally, more advanced debugging with breakpoints and inspecting registers and memory is possible through GDB or IDEs like Eclipse, VSCode, and Sublime.
Troubleshooting DAPLink and pyOCD
As an open source project, DAPLink and pyOCD require some debugging themselves. Top issues include:
- Interface firmware version mismatches
- Target power or clock errors
- Electrical issues on connections
- Incorrect interface configuration
- USB driver problems on host
- Python or OS environment problems
Thoroughly verifying target power and clocks as well as carefully checking pin connections and wiring alleviates the most common problems. The volunteer maintained forums and GitHub issues provide additional help resolving trickier issues with these open source tools.
Conclusion
For hobbyists and smaller teams, DAPLink provides an invaluable low cost avenue for debugging custom DesignStart Cortex-M1 SoCs. With care taken to properly configure connections, firmware, and host software, the full capabilities of the Cortex-M1 processor can be unleashed. Rapid prototyping and development is possible without expensive development boards or debug hardware.
