Cortex-M0 hangs after performing soft reset

A soft reset is a common troubleshooting technique used with Cortex-M0 microcontrollers to clear errors and reset the device to a known good state without fully powering down. However, some users have reported issues where the Cortex-M0 appears to hang or become unresponsive after a soft reset is performed.

What causes the Cortex-M0 to hang after a soft reset?

There are a few potential root causes that could lead to the Cortex-M0 hanging after a soft reset:

• Corrupted system clock – The system clock provides the heartbeat for the Cortex-M0’s operations. If it becomes corrupted or unstable, the processor may exhibit strange behaviors like hanging.
• Faulty reset circuitry – Issues with the reset circuitry on the board can lead to an incomplete reset that fails to properly restart the Cortex-M0.
• Problematic firmware – Bugs, infinite loops, or exceptions in the firmware running on the Cortex-M0 could cause it to hang when reset.
• Peripheral misconfiguration – Incorrect configurations of peripherals like timers, serial ports, or interrupts could trip up the reset sequence.
• Memory errors – Corruption of program code or critical data stored in memory could cause the processor to hang when reset.

How to troubleshoot a Cortex-M0 that hangs after soft reset

Debugging a hung Cortex-M0 after soft reset can be tricky, but here are some steps to isolate the issue:

1. Verify power supplies – Use a multimeter to check for any drops or noise on the microcontroller’s core, I/O, or peripheral supplies during reset. Power issues can manifest as hangs.
2. Check reset line – Probe the reset line to see if the reset pulse is being properly asserted and de-asserted. A scope or logic analyzer can help here.
3. Simplify application code – Minimize the amount of code running on reset by removing initialization of unused peripherals. This eliminatesfirmware-related hangs.
4. Initialize peripherals – Explicitly initialize peripherals like timers, serial ports, interrupts to known states before reset. This avoids configuration issues.
5. Skip clock initialization – If possible, have the Cortex-M0 boot up on a default clock setting rather than reconfiguring clocks on reset.
6. Disable interrupts – Temporarily disable interrupts during reset and see if that allows the processor to restart cleanly.
7. Use JTAG/SWD – Connect a JTAG or SWD debugger and step through reset handling code path to identify any crashes, infinite loops, or waits.
8. Simplify clock tree – Remove unused clock sources and PLLs from the reset clocking scheme. Simpler is better when unstable clocks could be an issue.
9. Check memory – Use built-in ECC or parity to detect any memory corruption. Consider reloading key sections of code from ROM rather than RAM.

Best practices for robust reset handling on Cortex-M0

Some design and firmware practices can help avoid issues with hanging on resets:

• Keep reset logic simple – Avoid complex clock switching or peripheral reconfiguration on reset. Initialize minimally.
• Handle clock failure – Implement clock failure detection code to catch unstable oscillator or PLL scenarios.
• Watchdog timers – Use watchdog timers to catch any microcontroller lock ups and safely reset the system.
• Defensive coding – When accessing registers or memory, double check configurations before writing. Validate input data.
• Tightly control interrupts – Disable or carefully manage interrupt sources during reset handling code.
• Isolate reset domains – Partition reset logic and power supplies for core, peripherals, and I/Os to contain issues.
• Fail-safe defaults – Define safe default values for registers and memory regions that get applied on reset.
• Reset test mode – Have a special reset test mode that simplifies application for debugging hangs.
• Log reset details – Log reset source, clock frequencies, register values to help post-mortem debugging of hangs.

Recovery procedures for a hung Cortex-M0

If all else fails and the Cortex-M0 remains hung after soft reset, some recovery procedures to consider are:

• Hardware reset – Assert the external reset pin low to force a hard reset and restart the microcontroller.
• Power cycle – Completely power down and cycle power to the board to return to a pristine state.
• Watchdog reset – Let the watchdog timer escalate to reset the system if enabled.
• JTAG / SWD reset – Issue JTAG or SWD soft reset commands which bypass on-chip reset logic.
• JTAG / SWD halt – Halt the core via JTAG or SWD, inspect state, and restart execution.
• Factory reset – Some boards have a dedicated factory reset function to fully reinitialize all hardware.
• ROM bootloader – Invoke ROM bootloader to reflash firmware or launch recovery routines.
• Backup firmware – Switch to a known good firmware image stored separately from main application firmware space.

Conclusion

A Cortex-M0 hanging after performing a soft reset can certainly be frustrating to debug. But methodically checking power, clocks, interrupts, default configurations, and the reset handling code itself can help uncover what is interrupting the proper reset sequence. Leveraging design techniques like separate reset domains, defensive coding, and logging can make systems more robust and easier to debug. And finally, understanding reset recovery procedures like hardware pin resets gives you an effective last resort to revive an unresponsive microcontroller.