Cortex-M Exception Handling and Return Mechanism

The Cortex-M processor implements robust exception handling capabilities to respond to events like exceptions, interrupts, and faults during program execution. The processor automatically saves context, executes exception handlers, and restores context upon return from an exception. This allows Cortex-M based systems to handle exceptions safely and recover program execution.

Cortex-M Exception Types

There are several types of exceptions in Cortex-M processors:

• Resets – Occur on power up or external reset signal
• NMI – Non Maskable Interrupt caused by critical events
• HardFault – For unrecoverable runtime errors like bus faults
• MemManage – Memory protection violations like MPU faults
• BusFault – Memory/bus data transfer errors
• UsageFault – Invalid instruction or data access
• SVCall – Supervisor call using SVC instruction
• DebugMonitor – Triggered on debug events
• PendSV – Pendable request for system service
• SysTick – System timer events
• Interrupts – triggered by peripheral modules

These different exception types allow handling various events and errors during program execution in an appropriate manner. The processor initiates a specific sequence of saving context, executing handler code, and restoring context tailored to each exception type.

Cortex-M Exception Model

The Cortex-M exception model consists of the following key components:

• Exception Vector Table – located at base address 0x0000.0000, contains entry points for exception handlers.
• Interrupt Control State Register – enables/disables interrupts.
• Stack Pointers – MSP for thread mode, PSP for handler mode.
• Link Register – to save return address for exception handlers.
• Exception Frame – stored on stack during exception entry.
• Exception Return – load stack frame and return on exception exit.

This architecture provides a structured mechanism to handle exceptions and return to normal program flow. The processor automatically stores context, calls handler code, and restores context by utilizing these hardware resources.

Exception Entry Sequence

When an exception occurs in Cortex-M, the following sequence is executed by hardware:

1. Complete execution of current instruction.
2. Disable interrupts by clearing PRIMASK if the exception is not NMI.
3. Save EXC_RETURN code in LR to return to current context later.
4. Save stack pointer in MSP or PSP based on handler mode.
5. Save exception frame on stack – xPSR, PC, LR, R12, R3-R0.
6. Load stack pointer for handler – MSP in thread mode, PSP in handler mode.
7. Clear pending servicing for PendSV if it was pending.
8. Fetch and execute handler code from vector table entry.

This well defined sequence preserves the system state information on the stack and loads the stack pointer and link register with information needed to return after exception handling.

Exception Frame

The exception frame saved on the stack contains:

• xPSR – Program status register with interrupt disable flags
• PC – Program counter value after completing last instruction
• LR – Link register value to return to current context
• R12, R3-R0 – Callee saved registers

The stack pointer value before exception entry is also stored in MSP or PSP. This stacked exception frame contains the information needed to restore context when returning from the exception handler.

Exception Handler

The exception handler code performs the following tasks:

1. Save remaining context – Stacked frame does not save R4-R11.
2. Clear exception status flags and handlers.
3. Perform exception handling – e.g. clear error sources.
4. Determine return strategy – return, reset, or escalate.
5. Restore context from stack frame.
6. Execute exception return to previous context.

The handler runs on the stack selected during exception entry and can leverage the stacked exception frame. It handles the exception condition appropriately and prepares for return to normal operation.

Exception Return

To return after exception handling, the handler executes an Exception Return instruction to:

• Reload stack pointer with value before exception entry.
• Reload PC with LR to return to point after last completed instruction.
• Reload xPSR to restore interrupt disable flags.
• Reload callee saved registers R12, R3-R0 from stack.

This restores the entire context that was stacked automatically during exception entry. The Exception Return instruction is tailored by hardware based on the return strategy – Thread mode, Handler mode, exception escalation etc.

Tailored Exception Return

Based on the return strategy, the processor modifies the Exception Return instruction behavior:

• Thread Mode – Reload MSP, clear execution priority.
• Handler Mode – Reload PSP and return to handler context.
• Exception Escalation – Modify return information to activate another exception.
• Clear Pending – Clear pending exceptions like PendSV.

This enables automated context saving, custom exception handling, and context restoring for robust exception management in Cortex-M processors.

Summary

• Cortex-M handles exceptions like interrupts, faults, and errors with a structured exception model.
• The processor automatically stacks context, calls handler, then restores context.
• Tailored exception entry, customized handling, and exception return provide robust exception management.
• This enables responsive exception processing and recovery of normal program execution.

In summary, the Cortex-M exception handling and return mechanism enables robust and efficient exception processing in embedded applications. The tailored automation by hardware simplifies exception management for developers.