David Moore

104 Articles

Bootloading Cortex-M1 with RTX Application

Booting a Cortex-M1 processor with an RTX real-time operating system (RTOS) application requires careful configuration of the processor's boot sequence

David Moore 8 Min Read

Running RTX code from external RAM vs ITCM on Cortex-M1

When developing applications for Cortex-M1 based microcontrollers, one important decision is where to place the RTX RTOS code - either

David Moore 7 Min Read

Using ST-Link debugger with Cortex-M1 FPGA design

The ST-Link debugger is an extremely useful tool for debugging and programming Cortex-M microcontroller designs implemented in an FPGA. By

David Moore 6 Min Read

Optimizing 32×32 bit Multiplication on Cortex-M0/M0+/M1

Performing fast 32-bit multiplications is crucial for many embedded and IoT applications using Cortex-M0/M0+/M1 chips. This article provides an in-depth

David Moore 4 Min Read

Tips on Implementing Cortex-M1 Bootloader

Implementing a bootloader for Cortex-M1 chips allows greater control and customization of the startup process. A properly implemented bootloader can

David Moore 12 Min Read

Modifying Stack Pointer (SP) and Program Counter (PC) in Cortex-M1

The stack pointer (SP) and program counter (PC) are important registers in the Cortex-M1 processor that control program execution flow.

David Moore 6 Min Read

What are Helium vector instructions in Arm Cortex-M series?

Helium vector instructions are a new set of SIMD instructions introduced in Arm Cortex-M55 that provide significant performance improvements for

David Moore 7 Min Read

What is Data Cache in Arm Cortex-M series?

The data cache in Arm Cortex-M series microcontrollers is a small, fast memory that stores copies of data from the

David Moore 9 Min Read

What is Instruction Cache in Arm Cortex-M series?

The instruction cache in ARM Cortex-M series microcontrollers is a small, fast memory that stores recently accessed instructions to improve

David Moore 9 Min Read

What are Stack Limits in Arm Cortex-M series?

The stack limits in Arm Cortex-M series microcontrollers refer to the maximum stack size available for each software thread or

David Moore 6 Min Read

Best practices for Cortex-M1 MMI generation in Xilinx FPGAs

Generating the Memory Mapped Interface (MMI) for a Cortex-M1 processor inside a Xilinx FPGA can be challenging if not done

David Moore 4 Min Read

Optimizing make_mmi_file.tcl Generation Time for Cortex-M1 Systems

Generating the make_mmi_file.tcl script is a key step in building applications for Cortex-M1 systems, but it can be time consuming.

David Moore 6 Min Read
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