David Moore

104 Articles

Strongly Ordered Memory in Armv6 and Armv7 (Explained)

Strongly ordered memory is a memory ordering model used in the ARMv6 and ARMv7 architectures to ensure correctness and consistency…

David Moore

6 Min Read

Arm

Unified vs Separate Memory Address Spaces in ARM Cortex-M

ARM Cortex-M processors can be configured with either a unified or separate memory address space for code and data. The…

David Moore

9 Min Read

Arm

Modified Harvard Architecture in ARM Cortex-M Chips

The ARM Cortex-M series of microcontroller chips utilize a modified Harvard architecture. This architecture separates instruction and data memories into…

David Moore

18 Min Read

Arm Cortex M3

What is the Thread mode in Arm Cortex M3?

The Thread mode in Arm Cortex M3 refers to one of the processor modes that controls access privileges in the…

David Moore

9 Min Read

Arm

Demystifying Arm’s Branch and Link Instructions (BL and BLX)

The Arm architecture includes two important branch and link instructions - BL and BLX. These instructions allow you to branch…

David Moore

9 Min Read

Arm

Measuring interrupt latency on Arm Cortex-M processors

Interrupt latency is an important performance metric for real-time embedded systems built around Arm Cortex-M processors. It refers to the…

David Moore

7 Min Read

Arm

Changing Processor Modes on ARM with CPSR Writes

The ARM processor has several different processor modes that allow access to different resources and functionality. The current processor mode…

David Moore

11 Min Read

Arm

Processor Modes and Mode Control in the ARM CPSR

The ARM CPSR (Current Program Status Register) controls the processor operating mode and enables switching between different modes in ARM…

David Moore

13 Min Read

Arm

What are the the Application Program Status Register (APSR) in Arm Cortex-M

The Application Program Status Register (APSR) in Arm Cortex-M is a 32-bit register that contains application-level status and control information.…

David Moore

8 Min Read

Arm Cortex M4

Reducing Load/Store Instruction Latency on Cortex M4

The Cortex-M4 processor is designed to provide high performance and low power consumption in embedded applications. However, the load and…

David Moore

7 Min Read

Arm

NVIC Registers Explained – ISER, ICER, ISPR, ICPR

The NVIC (Nested Vectored Interrupt Controller) registers ISER, ICER, ISPR and ICPR are used to enable, disable, set pending, and…

David Moore

11 Min Read

Arm Cortex M4

Understanding Pipeline Hazards in Cortex-M4 Microcontrollers

The Cortex-M4 processor implements a 3-stage pipeline to improve performance by allowing multiple instructions to be processed simultaneously. However, pipeline…

David Moore

8 Min Read

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