The ARM fault status register is a key register in ARM processors that provides information about exceptions and faults that have occurred during program execution. This register plays a critical role in exception and fault handling on ARM-based systems.
When an exception or fault occurs, the ARM processor automatically saves information about the event in the fault status register. This includes details like the type of fault, the faulting instruction address, the processor mode at the time of the fault, and status flags. By examining this register, the exception handler can determine how to appropriately handle the fault and recover normal program execution.
Purpose and Overview
The main purposes of the ARM fault status register are:
- Indicate that an exception or fault has taken place
- Identify the type of exception or fault
- Provide the program counter value at the time of the fault
- Indicate the processor mode when the fault occurred
- Provide status flags detailing the fault
This information helps the exception handler take the right actions to resolve the fault and resume correct program operation. The register is updated synchronously on taking an exception before the exception vector is entered.
The fault status register is a 32-bit read-only register present in all ARM processors. Its contents provide a snapshot of the state when the last exception occurred. The layout of the register bits and fields is consistent across different ARM architectures like ARMv7 and ARMv8.
Fault Status Register Format
The fault status register contains the following major bitfields:
- Exception Type: Bits [31:16] indicate the exception type, e.g. reset, data abort, prefetch abort, etc.
- Fault Status Code: Bits [15:12] provide the fault status code with additional details like the access type for aborts.
- Instruction Length: For synchronous aborts, indicates the size of the instruction that caused the abort.
- Mode: Bits [4:0] specify the processor mode at the time of the exception, e.g. User, FIQ, IRQ, Supervisor, etc.
Other bitfields provide information like whether the instruction was Thumb or ARM, and cumulative exception status flags.
Accessing the Fault Status Register
To access the fault status register, the exception handler can read the register directly using:
MRC p15, 0, <Rd>, c5, c0, 0;
Where <Rd> is the destination register to read the contents into. For example:
MRC p15, 0, R0, c5, c0, 0;
This Coproccesor 15 access will load the fault status register value into R0. The handler can then analyze the register fields to determine the fault cause and handling actions.
Usage in Exception Handling
When an exception occurs, the ARM processor automatically does the following key steps:
- Saves program state like register contents
- Updates the fault status register with exception details
- Loads the exception vector address into the PC
- Starts executing the exception handler code
The handler can then examine the fault status register to identify the exception and cause. Key usage scenarios include:
- Data Abort Handler – Checks the fault status code to identify issues like translation faults, permission faults, alignment faults, etc. It takes suitable actions like fixing invalid translations, handling permission errors, etc.
- Prefetch Abort Handler – Identifies the aborting instruction using the fault address and fixes potential issues like invalid instructions, invalid memory access, etc.
- Interrupt/Exception Handler – Identifies the interrupt or exception source using the exception type field and handles it appropriately by running the right interrupt service routine.
Without the fault status register, the exception handler would have no information about the fault and would not be able to reliably handle it and recover program execution. The register is thus vital for robust exception handling on ARM platforms.
Typical Fault Status Values
Here are some typical fault status register values returned for common exceptions and faults:
- Reset – 0x000004, indicates a processor reset
- Undefined Instruction – 0x000014, invalid instruction execution in User mode
- Prefetch Abort – 0x00000C, indicates an instruction prefetch abort
- Data Abort – 0x000008, indicates abort during a data access
- IRQ – 0x000018, normal interrupt request in User mode
- FIQ – 0x000011, fast interrupt request in FIQ mode
The fault status values provide an indication of the exception category as well as the processor mode. The handler examines the value to identify and handle the specific exception or fault.
Some common issues related to the ARM fault status register include:
- Forgetting to read the register in the exception handler, leading to unidentified faults.
- Not clearing the register after handling the fault, so the same stale value keeps reappearing.
- Improper handling when multiple exceptions occur close together, corrupting register contents.
- Trying to access the fault register from User mode, which results in an exception.
- Incorrectly configuring the register in Debug state.
Proper initialization of the register, careful saving of context during nested exceptions, and good register management in exception handlers can help avoid these pitfalls.
Relation to Other Registers
The fault status register complements other related registers in ARM processors:
- The Fault Address Register holds the memory address of the instruction that caused a fault.
- The Vector Address Register indicates the start of the exception handler.
- The Saved Program Status Register stores the CPSR value at exception entry.
These registers together provide a detailed picture of the exception state. The handler examines them in conjunction while handling faults and exceptions.
In summary, the ARM fault status register plays a key role in exception handling by providing crucial details about faults like the faulting type, instruction address, processor mode, and status flags. This helps guide the exception handler’s actions for robust fault resolution and recovery. Proper usage of this register is essential for building reliable exception handling routines on ARM-based platforms.