The ARM Cortex-M4 is a 32-bit processor core designed for embedded applications requiring high performance and low power consumption. It implements the ARMv7-M architecture and includes features like digital signal processing (DSP) instructions, single cycle multiply and divide operations, memory protection unit (MPU), and nested vectored interrupt controller (NVIC).
Like all ARM Cortex-M cores, the Cortex-M4 has a simplified register set compared to application processors like Cortex-A series. However, it still contains several important registers that programmers need to understand in order to make efficient use of the processor.
The Cortex-M4 core registers provide information about the processor state and allow modifying certain behaviors.
The program counter (PC) holds the address of the current instruction being executed. It is 32 bits wide and increments by 4 bytes after each instruction fetch. The processor automatically updates the PC, but it can also be modified directly through branch instructions, exception entries, and returns from interrupts.
Program Status Register
The program status register (PSR) contains condition code flags like negative, zero, carry, and overflow that are set based on the results of arithmetic and logical instructions. This allows subsequent instructions to perform conditional execution based on the flags. The PSR also includes the current execution state and interrupt masking bits.
The stack pointer (SP) holds the address of the top of the stack. It is used for pushing and popping stack frames during function calls. The SP is banked for each exception handler so that each has its own stack space.
The link register (LR) stores the return address when a branch with link instruction is executed. This allows exception handlers to save the return address so execution can resume after handling the exception.
The Cortex-M4 includes several special registers like the CPU ID register for identifying the core version, debug halt register for halting execution, and fault status registers for debugging exceptions.
System Control Registers
The system control registers are used for configuring the memory system, enabling peripherals, and managing low power operation.
Memory Control Registers
The memory control registers dictate things like cache policies, memory access timings, endianness, and Flash patch control. For example, the flash access control register can enable prefetch and caches for instruction and data accesses.
Clock Control Registers
The clock control registers allow enabling/disabling clocks for different peripherals. This allows unused peripherals to be powered down to save energy. The registers control high and low speed clocks derived from the CPU clock.
Power Control Registers
The power control registers are used to manage different low power modes like sleep, deep sleep, and standby. They indicate which power mode the system is in and control transitions between modes.
The nested vectored interrupt controller (NVIC) handles prioritizing and dispatching interrupts in the Cortex-M4. Its registers are used for configuring interrupts and reading pending or active interrupts.
Interrupt Set Enable Registers
These registers enable interrupts by setting the corresponding bit for the interrupt. Multiple interrupts can be enabled simultaneously by setting multiple bits.
Interrupt Clear Enable Registers
These registers disable interrupts by clearing the bit for the corresponding interrupt number. Multiple interrupts can be disabled at once.
Interrupt Priority Registers
These registers hold the priority level for each interrupt. The NVIC uses this to determine which pending interrupt gets serviced first if multiple interrupts are pending.
Interrupt Pending Registers
These read-only registers indicate which interrupt sources are currently pending, meaning their event trigger has occurred but the interrupt handler has not yet executed.
SysTick Timer Registers
The Cortex-M4 contains a 24-bit SysTick timer for generating periodic interrupts at a programmed interval. This provides a simple way to handle periodic tasks or software timers.
SysTick Control and Status Register
This register is used to enable the SysTick timer, choose the clock source, check if it has counted to zero, and generate interrupts on timeout.
SysTick Reload Value Register
This sets the timeout value that causes the timer to reset to zero and optionally generate an interrupt when reached.
SysTick Current Value Register
This read-only register contains the timer’s current value. It decrements each clock cycle and resets to the reload value on timeout.
The Cortex-M4 FPU provides single and double precision floating point support. Its registers hold floating point values and FPU-specific control and status information.
Floating Point Status and Control Register
This register reports error conditions like invalid operation, divide by zero, overflow, etc. It also controls behaviors like default NaN mode.
Floating Point Exception Register
This read-only register provides details on the cause of a floating point exception like invalid operation, divide by zero, inexact, etc.
Media and FP Feature Registers
These indicate what optional FPU features are implemented, such as half-precision support and divide instructions.
The FPU has 32 single-precision and 32 double-precision registers for holding floating point values during computations.
The debug registers are used by the debug module to set watchpoints, breakpoint, capture data, and control execution while debugging.
Debug Halting Control and Status Register
This can halt execution on debug events or software request. Status flags indicate the cause of a debug halt.
Debug Core Register Selector Register
Selects which core register contents to transfer to/from the debug module for examination.
Debug Core Register Data Register
Allows reading or writing the contents of the core register selected by the debug selector register.
Debug Exception and Monitor Control Register
Controls entry to and exit from debug state. Also enables debug monitor mode which makes debug exceptions non-maskable.
Debug Watchpoint Registers
Watchpoints trigger debug halt when an access (read/write) matches the address in the watchpoint register.
Memory Protection Unit Registers
The optional memory protection unit (MPU) allows defining regions of memory with individual access permissions. This prevents privileged software from accessing protected regions.
MPU Type Register
Indicates number of supported regions and subregions in the MPU.
MPU Control Register
Globally enables the MPU and controls default memory map behavior.
MPU Region Registers
Define the base address, size, access permissions, and memory attributes for each MPU region.
MPU Alias Registers
Optional registers that allow overlapping MPU regions with unique aliases to enforce permissions on common memory areas.
In summary, the Cortex-M4 registers provide control over all aspects of the processor. Understanding how to properly configure these registers is key to building efficient embedded applications on the Cortex-M4 platform.