The ARM Cortex M0 is a 32-bit RISC processor core designed for microcontroller applications. It is the smallest and most basic member of the Cortex-M family of cores. The Cortex M0 memory map defines how memory is organized and accessed on Cortex M0 based microcontrollers.
Cortex M0 Memory Organization
The Cortex M0 has a simple, linear physical address space of 32 bits. This means it can theoretically access up to 4GB of memory. However, the actual amount of memory available depends on the specific microcontroller implementation.
The 4GB address space is divided into the following regions:
- Code (Flash): Stores program code
- SRAM: Stores data
- Peripherals: Maps device peripherals into memory space
- External memory: Additional external memories like external RAM/Flash
The exact sizes and locations of these regions vary between different Cortex M0 microcontrollers. But the general organization remains the same.
Code Memory Region
The code or flash memory region stores the executable program code. It is typically made up of internal flash memory embedded within the microcontroller itself. But it could also be external flash.
On microcontrollers with a Harvard architecture, code memory is physically separate from SRAM. The Cortex M0 implements a modified Harvard architecture, which allows code and data to reside in a single unified address space.
The size of internal flash varies greatly between Cortex M0 chips. It can range from just 32KB to over 1MB. External flash can provide additional storage if required.
Code memory is located at the start of the physical address space, starting at address 0x0000_0000. It extends up to the start of the SRAM region.
The region is read-only and can only be modified through special flash programming operations.
SRAM Memory Region
The SRAM memory region stores global and static variables used by the program. It provides general purpose read/write storage for data.
SRAM size ranges from 4KB to over 100KB on different Cortex M0 microcontrollers. The SRAM region occupies the address space immediately after the flash memory region.
For example, on a device with 32KB flash and 8KB SRAM, the SRAM region would start at 0x0000_8000 and extend up to 0x0000_BFFF.
SRAM can be read and written freely by code, and maintains its contents even when power is removed, making it useful for storing data that needs to persist.
Peripheral Memory Region
The peripheral memory region maps various built-in peripherals of the microcontroller into the processor’s physical address space.
This allows peripherals to be access similarly to SRAM using load and store instructions. Registers of peripherals like GPIO, timers, UARTs, ADCs etc are mapped into this region.
The exact mapping is specific to each microcontroller and its peripherals. But peripherals are typically located after the SRAM region.
For example, the GPIO peripheral registers may be mapped at 0x4000_0000. While the timer registers are at 0x4000_1000. This allows them to be read/written easily.
Accesses to unused peripheral addresses are ignored. Trying to access a peripheral not present on a particular MCU simply does nothing.
External Memory Region
The external memory region located at the end of the 4GB address space is used to access external memories like external RAM and external flash.
External memories can provide much more storage capacity compared to the limited internal SRAM and flash. Slow external memories can be used for data storage, while fast memories provide RAM expansion.
The external memory region is optional and may not actually be implemented on some Cortex M0 chips. The maximum address size for a Cortex M0 core is limited to 1MB without an external bus interface.
With an external bus interface, the 32 bit address bus allows access to the full 4GB address space. Memories like SPI Flash and parallel RAM/flash can be accessed in this region.
Reserved Regions
There are some reserved regions in the Cortex M0 memory map that don’t correspond to any actual memory or peripheral. These reserved regions should not be accessed by code.
For example, the addresses from 0xE004_E000 to 0xE005_0FFF are reserved and attempting to access this region may result in a hard fault or other exception.
Reserved regions exist to allow later versions of ARM Cortex-M cores to expose new features that can be mapped into these unused areas. Accessing them on current cores causes an error.
Cortex M0 Memory Map Example
Here is an example memory map for a hypothetical Cortex M0 microcontroller:
- 0x0000_0000 – 0x0003_FFFF: 64KB Flash Memory (Code)
- 0x2000_0000 – 0x2000_FFFF: 64KB SRAM (Data)
- 0x4000_0000 – 0x4001_FFFF: Peripherals (GPIO, UART, timers etc)
- 0x4002_0000 – 0x4002_FFFF: External 8MB SPI Flash Memory
- 0xE000_0000 – 0xE001_FFFF: Reserved Region
This shows the different memory regions that make up the 4GB physical address space of a Cortex M0 microcontroller. The exact sizes and positions vary between different chips.
Accessing Cortex M0 Memory
There are a few different ways code can access memory regions in the Cortex M0 memory map:
- Flash memory – Executed by fetching code instructions
- SRAM – Read/write using load/store instructions
- Peripheral registers – Special load/store instructions
- External memory – Memory mapped access
For SRAM and flash memories, standard ARM Thumb/Thumb2 load/store instructions like LDR, STR allow access via registers or addressing modes.
Peripheral registers are accessed using memory mapped I/O. The MRS, MSR, LDR and STR instructions target specific peripheral register addresses.
External memories are also accessed by directly reading/writing to external memory addresses. Higher latency allows use of slower memories.
So in summary, the Cortex M0 memory map allows uniform access to different types of memories by mapping them into the linear 4GB address space.
Summary
The ARM Cortex M0 memory map defines the logical organization of the processor’s 4GB physical address space. Different regions are mapped to internal flash, SRAM, peripherals and external memory.
Understanding how the microcontroller’s memory resources are mapped allows you to better utilize them in your programs. The memory map provides a useful reference for any Cortex M0 developer.
