ARM Cortex M Registers

ARM Cortex-M processors contain a number of key registers that are essential for programming and interacting with the core. These registers control critical functions like interrupts, exceptions, power modes, and core peripherals. Understanding the role of each register is important for effectively utilizing the Cortex-M processor.

Program Status Register

The program status register (PSR) contains important status and control bits for the Cortex-M core. This is a 32-bit register that is accessible in both user and privileged modes. The PSR contains the following bit fields:

• N, Z, C, V bits: These flag bits reflect the results of arithmetic and logical instructions.
• Q bit: This reflects the saturation state of some DSP instructions.
• GE bits: Greater than or Equal flags used for DSP instructions.
• Interrupt disable bits: Used to disable interrupts globally or from privileged code only.
• APSR, IPSR, EPSR: These fields contain the application, interrupt, and execution program status respectively.
• T bit: Used to indicate Thumb state (always 1 on Cortex-M).

The PSR is used for almost any context switching or exception handling on the Cortex-M processor. It must be preserved and restored when changing states.

Control Register

The control register (CONTROL) configures core behaviors like thread mode, stack alignment, memory endianess, and vector table location. The key fields of the CONTROL register include:

• nPRIV: Configures Thread mode as privileged or unprivileged.
• SPSEL: Selects main stack pointer or process stack pointer.
• nVPN: Controls location of vector table in code memory.
• STKALIGN: Sets 8-byte or 4-byte stack alignment.
• ENDIANESS: Selects little or big endian memory accesses.

The CONTROL register settings remain in effect until the core is reset. This register is normally configured at early boot time and not modified again.

Vector Table Offset Register

The vector table offset register (VTOR) contains the address of the exception vector table. This table contains the entry points for all exception and interrupt handlers. On reset, the VTOR is initialized to point to the start of flash memory.

The VTOR can be modified dynamically to relocate the vector table to RAM or to support multiple vector tables. This register is 32 bits wide and aligns the vector table on a 256 byte boundary.

Application Interrupt and Reset Control Register

The application interrupt and reset control register (AIRCR) is used for major interrupt related functions like:

• Setting priority grouping of exceptions
• Triggering a system reset
• Altering the priority threshold for exception triggering
• Enabling/disabling interrupts in the vector table

This register receives the incoming interrupt number when an IRQ or exception is triggered. The processor reads the AIRCR register to determine whether to service the interrupt based on priority thresholds.

System Control Register

The system control register (SCR) controls entry into key system critical states like thread mode, sleep mode, and exception handling.

The SCR fields include:

• SLEEPONEXIT: Enters sleep state after exception return
• SLEEPDEEP: Selects sleep or deep sleep state
• SEVONPEND: Wakes processor on pending interrupt while sleeping

Modifying the SCR fields allows optimizing for low power consumption in embedded applications built around the Cortex-M cores.

Memory Protection Unit Registers

The Memory Protection Unit (MPU) registers can enforce privilege and memory access rules set by the programmer. These include:

• MPU Type Register: Specifies MPU features
• MPU Control Register: Globally enables MPU and sets background region
• MPU Region Number Register: Specifies number of supported regions
• MPU Region Base Address Register: Sets protected region base address
• MPU Region Attribute and Size Registers: Configures region bounds and access rules

Using the MPU registers allows creating a robust privilege and memory access control scheme tailored for a specific application.

Nested Vectored Interrupt Controller

Cortex-M processors integrate the Nested Vectored Interrupt Controller (NVIC) for managing external interrupts from peripherals. The NVIC registers provide extensive flexibility in handling interrupts, including:

• ISER: Interrupt Set Enable Register to enable specific interrupts
• ICER: Interrupt Clear Enable Register to disable interrupts
• ISPR: Interrupt Set Pending Register to trigger interrupts manually
• IPR: Interrupt Priority Registers to assign priority levels

NVIC gives full control over interrupt handling, preemption, tail-chaining, and priority grouping for fast, responsive interrupt servicing.

System Timer Registers

The Cortex-M processors contain an integrated SysTick timer for generating periodic interrupts, useful as a real-time clock. The main SysTick registers are:

• SYST_CSR: Control and status register
• SYST_RVR: Reload value register sets timer interval
• SYST_CVR: Current value register indicates current timer value

The SysTick timer runs off the core clock and can precisely time events with low overhead. It’s commonly used for RTOS ticks or high resolution timers.

Data Watchpoint and Trace

The embedded trace macrocell (ETM) provides instruction and data tracing capabilities. The main registers controlling ETM behavior are:

• ETM Control Register: Enables tracing and timestamping
• ETM Trigger Event Register: Starts and stops trace capture
• ETM View Data Register Sets: Selects data values to trace
• ETM ViewInst Register Sets: Selects instructions to trace

ETM tracing provides powerful runtime debugging by non-intrusively monitoring code execution without halting the core.

Floating Point Unit Registers

Cortex-M4 and M7 cores include an optional single precision floating point unit (FPU). The FPU has a full set of registers for floating point calculations:

• FP Control and Status Registers: Manage FPU exceptions and rounding modes.
• FP Instruction Registers: Hold in-flight instructions.
• FP Data Registers: 32 single precision registers for computation.

The FPU registers give the higher Cortex-M cores true single precision math capabilities for applications like digital signal processing and 3D graphics.

Debug Registers

Cortex-M cores integrate debug components like breakpoints and watchpoints. The registers used for debugging include:

• Debug Halting Control and Status Register: Manages debug events
• Debug Fault Status Register: Logs faults like memory faults
• Debug Core Register Selector Register: Selects core registers for debugging
• Debug Core Register Data Register: Holds core register contents

These debug registers enable non-intrusive debugging of running firmware for rapid development and troubleshooting.

In summary, mastering the key ARM Cortex-M registers allows taking full advantage of the processor’s capabilities in areas like power management, real-time responsiveness, memory protection, and debug visibility into firmware execution.