The Cortex-M3 processor implements the ARM Thumb-2 instruction set architecture, which includes 16-bit and 32-bit instructions. The 16-bit instruction set provides a rotate right (ROR) instruction but not a rotate left (ROL) instruction. The 32-bit instruction set does include both ROR and ROL instructions.
The main reason the 16-bit Thumb instruction set only has ROR and not ROL is efficiency and optimization for embedded applications. Rotate right is more commonly used than rotate left in most code, so having a single rotate instruction saves space. The barrel shifter hardware in the Cortex-M3 already supports left rotate internally, so a separate ROL instruction wasn’t needed. The 32-bit instruction set has fullfeatured rotate support with both directions.
Thumb Instruction Set Architecture
The original Thumb ISA was designed by ARM as a 16-bit compressed version of the 32-bit ARM instruction set for improved code density. Thumb code is able to achieve 65% higher density while maintaining much of the performance. The 16-bit encoding reduced overall code size and memory requirements, making it ideal for embedded systems.
The first generation of Thumb included mostly the most commonly used 32-bit ARM instructions but with 16-bit encodings. This included arithmetic, logical, branch and load/store instructions. To reduce the opcode space, some restrictions were imposed such as no shift operands in arithmetic instructions.
Thumb2 expanded the Thumb ISA with many more 32-bit instructions while retaining full backwards compatibility with the original Thumb ISA. This brought the capabilities much closer to the ARM ISA while still retaining the 16-bit encoding benefits. Branch instructions were improved, conditional execution support was added and many more 32-bit instructions like extra arithmetic and multiply instructions.
Limited Opcode Space
The main drawback of the 16-bit Thumb encoding is limited space for opcodes, the operation specifier for instructions. With only 16 bits to encode each instruction, there weren’t enough bits to include every single instruction. ARM had to carefully choose the most beneficial instructions and leave out the rest.
Having both rotate left (ROL) and rotate right (ROR) instructions would have taken up valuable opcode space for two instructions doing similar functions. Since ROR is more common, it was chose to be included. The opcode bit savings allows room for other beneficial instructions.
Optimized for Embedded Systems
Embedded systems have much different code requirements compared to general purpose software. They are optimized for efficiency, performance and small code size. The Thumb ISA was designed with embedded microcontrollers in mind as the primary application.
Typical embedded code has certain characteristics that guided the design of Thumb. Loops, branches and stack operations occur frequently. Arithmetic operations like adds, subtracts and compares are common, while multiplies and divides are relatively rare. Logical bitwise operations like AND, OR and XOR are also frequent.
In this context, ROR instructions see higher usage than ROL. Rotating bits right is a common operation for parsing bitfields, error checking, shifting values and aligning data. So ROR was included but not ROL to save space.
Hardware Support in Cortex-M3
The Cortex-M3 processor contains a barrel shifter as part of its arithmetic logic unit (ALU). This hardware can shift or rotate the operands as part of arithmetic and logical instructions. This shifter supports both left and right rotations efficiently in hardware.
So even without a ROL instruction, the processor can still perform left rotate operations using the barrel shifter. The compiler is able to use the ROR instruction along with adjustments to the shift amount to generate a left rotate operation in code.
Barrel Shifter Overview
A barrel shifter is a digital circuit that can shift or rotate binary values by a specified number of bits in one cycle. It consists of multiple stages of 2-to-1 multiplexers that select input bits from different positions based on the shift amount.
Rotation is performed by shifting and then wrapping the bits back around. Without a barrel shifter, software would have to do multiple shifts and mask out overflow bits to implement rotates. A hardware barrel shifter makes bit manipulation much faster and more efficient.
Supporting Left Rotates
The Cortex-M3 barrel shifter contains both left and right rotate capabilities that can be driven from the ALU during instruction execution. This means the ROR instruction can shift in either direction by controlling the shift amount.
A ROR by N bits is equivalent to a left rotate by 32-N bits on 32-bit values. The compiler automatically converts ROL operations to appropriate ROR instructions in the generated assembly code by inverting the shift amount.
So even without a ROL instruction, the Thumb ISA can still efficiently perform left rotates using the ROR instruction and barrel shifter hardware.
32-bit Thumb-2 Instructions
Thumb-2 provided a major expansion to the Thumb ISA with variable width instructions. It added many new 32-bit instructions so that many operations could be done using 32-bit encodings rather than multiple 16-bit instructions.
One of the main enhancements in Thumb-2 was full support for shifts and rotates in both directions. The 32-bit encoding allowed room for both ROR and ROL instructions.
32-bit Arithmetic Instructions
With Thumb-2, more complex arithmetic operations like multiplication could now be done using single 32-bit instructions instead of software routines or multiple 16-bit instructions. This improved performance.
The 32-bit instructions also added support for large shift amounts and rotates. The 16-bit shift instructions were limited to 5 bits of shift, but 32-bit allows shifts by registers.
Full Rotate Support
Thumb-2 added 32-bit variants for rotate right (ROR) and rotate left (ROL) with support for large rotation amounts. This provided full rotates without relying on the barrel shifter and compiler tricks.
With the dedicated ROL instruction, the compiler no longer needs to convert ROL into ROR when generating code. This simplifies assembly output and improves performance compared to the automatic transforms.
Usage in Compiled Code
In compiled C/C++ code, rotate operations are performed implicitly by the compiler and converted into appropriate Thumb or Thumb-2 instructions depending on context. This happens automatically based on data types and rotate amounts.
Bit Rotations
For bitwise rotations on smaller integer types like chars, shorts or ints, the compiler will use the 16-bit ROR instruction. This performs a right rotate by a 5-bit immediate amount.
To rotate left for these small types, the compiler inverts the shift amount to convert it to a ROR operation with equivalent behavior. This relies on the barrel shifter to provide the left rotate capability.
Register Rotations
For variable rotates or rotates on larger integer types like long long, the compiler will use the 32-bit Thumb-2 instructions. ROL and ROR are both available, so no tricks are needed.
For constant rotates, the compiler may optimize and use smaller 16-bit instructions where possible. But for general variables, the 32-bit encodings will be used.
Summary
In summary, the Cortex-M3 Thumb ISA only contains a rotate right instruction in the base 16-bit encoding due to the limited opcode space and typical usage in embedded programs. The barrel shifter hardware allows the processor to still perform left rotates efficiently.
The Thumb-2 extensions provide full rotate support with both rotate left and right in the 32-bit instructions. This improves performance while maintaining backwards compatibility for the vast amount of existing Thumb code.
By understanding the instruction set architecture evolution and hardware capabilities, we can see why the choice was made to have only ROR in the base Thumb ISA. The processor supports both rotation directions in an optimized way overall.
