What is Wake-up interrupt controller in Arm Cortex-M series?

The wake-up interrupt controller (WIC) in Arm Cortex-M series microcontrollers is a peripheral module that manages wake-up from low power modes. It allows the processor to be woken up from sleep and deep sleep modes when certain events or interrupts occur, enabling low power operation while still being able to respond to critical events.

Overview of Sleep and Deep Sleep Modes in Cortex-M

The Cortex-M processors have various low power or sleep modes to conserve energy when the system is idle. The two main modes are:

• Sleep mode – The CPU is stopped, but peripherals and SRAM remain powered.
• Deep sleep mode – The CPU and peripherals are powered off. Only SRAM and watchdog timer remain active.

In both these modes, any interrupt or event can wake up the processor to resume normal operation. The wake up sources can be external interrupts from GPIO pins, internal peripheral interrupts like timers, serial communication events etc. Managing these wake up sources and providing the ability to safely transition in and out of low power modes is the main function of the WIC.

Why is the Wake-Up Interrupt Controller Needed?

When the Cortex-M CPU enters sleep or deep sleep mode, it stops executing instructions and halts the clock to internal logic to save power. But the various peripherals and wake up sources remain active and can still generate interrupts or events. Without the WIC, these incoming interrupts would have nowhere to go because the core is sleeping, and could get lost or block subsequent interrupts. The WIC serves as an intermediary that can catch these interrupts and safely hold them until the CPU wakes up and is ready to handle them. Some key capabilities provided by the WIC include:

• Interrupt aggregation – Multiple incoming interrupts are consolidated and held until processor wake up.
• Interrupt prioritization – Higher priority interrupts can override lower priority ones using configurable priority schemes.
• Safe transition into and out of low power modes – The WIC handles synchronization to ensure no interrupts are lost during the transition.

Therefore, the WIC enables the Cortex-M CPU to properly sleep and conserve power without losing responsiveness to external events that need attention.

Key Hardware Components of the Cortex-M WIC

The WIC integrates closely with the Nested Vectored Interrupt Controller (NVIC) which manages interrupts in Cortex-M. The key hardware components that make up the WIC module are:

• Interrupt Hold Registers – These store pending interrupts when the processor is sleeping.
• Interrupt Mux – Arbitrates between normal NVIC interrupts and wake up interrupts from the Hold Registers.
• Interrupt Arbiter – Prioritizes the competing interrupts.
• Wake Up Detection Logic – Generates internal wake up signals to bring the CPU out of sleep mode.
• Interrupt Clear Logic – Clears interrupts from Hold Registers once they are processed.

How the Cortex-M WIC Works

Here is a simplified overview of how the WIC interacts with the NVIC and CPU to handle wake-up from sleep modes:

1. The CPU executes WFI or WFE instruction to enter sleep mode. Clock to CPU and logic is gated off.
2. A peripheral interrupt is triggered, but CPU cannot process it directly in sleep mode.
3. The interrupt is captured by the WIC Interrupt Hold Registers and queued for later handling.
4. If the interrupt priority exceeds the wake up threshold configured by software, the Wake Up Detection logic will trigger an internal wake up event.
5. This causes the CPU to resume execution. The WIC presents the pending interrupts to the NVIC/CPU via the Interrupt Mux.
6. Software handles the interrupts as normal. WIC Interrupt Clear logic removes them from Hold Registers.
7. The CPU can safely re-enter low power mode once interrupts are cleared.

For deep sleep mode, the WIC enables interrupts to remain latched during power down and restoration of peripherals, preventing them from getting lost before the CPU comes back up.

Software Interface for Configuring the WIC

The processor accesses the WIC through a memory-mapped interface. Key software configurable registers include:

• Interrupt Mask Registers – Enables or disables specific interrupts as wake-up sources.
• Interrupt Clear Registers – Write 1 to manually clear interrupts from Hold Registers.
• Interrupt Priority Threshold – Sets the priority level required for an interrupt to trigger a wake up event.

By programming these registers, software can customize the interrupts that are capable of waking the system, as well as tailor the priority and preemption behavior to the specific use case.

Benefits of the Cortex-M Wake-Up Interrupt Controller

In summary, the key benefits provided by the WIC peripheral in Cortex-M microcontrollers include:

• Enables implementation of sleep and deep sleep low power modes.
• Wake-up latency reduction since pending interrupts are cached.
• Prevents loss of interrupts during power state transitions.
• Configurable interrupt masking and prioritization.
• Simplifies software by handling wake-up interrupt aggregation and arbitration in hardware.

By providing robust support for wake-up from sleep modes while reducing interrupt latency and complexity, the WIC helps enable powerful low power designs using energy efficient Arm Cortex-M series microcontrollers.