The ARM Cortex-M3 is a 32-bit processor core that is widely used in embedded systems and IoT devices. Its memory layout is optimized for high performance and low power consumption. The Cortex-M3 has a Von Neumann architecture with a unified address space for both code and data. This article provides an overview of the different memory regions in the Cortex-M3 memory map and their purpose.
Cortex-M3 Memory Map Overview
The Cortex-M3 processor has a 4GB memory address space, split into the following regions:
- Code region: Stores program code and read-only data.
- SRAM region: Stores variables and stack. On-chip SRAM is located here.
- Peripheral region: Maps to memory-mapped peripherals.
- External memory region: External memories like RAM and flash are mapped here.
- Private peripheral bus region: Maps to system control registers.
The exact size of each region varies based on the Cortex-M3 implementation. But the general layout provides segmentation and protection for different types of memory accesses.
Code Region
The code region occupies the bottom 256MB of the address space, from 0x00000000 to 0x0FFFFFFF. It is used to store executable program code and read-only data like constants and strings.
On most Cortex-M3 chips, the on-chip flash memory is mapped to the code region. The flash size can vary from 128KB to multiple MB. Small amounts of RAM or ROM may also exist in the code space for temporary data storage.
The code region is meant for read-only access during normal operation. Write access triggers a fault exception. This protects program code from accidental overwrite.
SRAM Region
The SRAM region occupies the next 256MB, from 0x10000000 to 0x1FFFFFFF. This region holds the Cortex-M3’s internal SRAM used for data variables and the stack.
Typically between 16KB to 128KB of SRAM is present on-chip. Larger amounts of external SRAM can also be added in this address space. The stack pointer is set to the top of the SRAM region and grows downwards.
The SRAM region provides fast access for volatile data storage and execution. Variables can be read and written freely. The stack organizes local variables and function parameters.
Peripheral Region
The peripheral region occupies 512MB from 0x40000000 to 0x5FFFFFFF. As the name suggests, this region maps various peripheral modules present on the Cortex-M3 chip.
Typical peripherals include GPIO, timers, UART, I2C, SPI, ADC, DAC, and more. Their control registers are memory-mapped into the peripheral region. Each peripheral gets its own address range.
Reading and writing to locations in the peripheral region accesses the peripheral registers. This allows flexible peripheral control from software.
External Memory Region
The external memory region from 0x60000000 to 0x9FFFFFFF maps additional memories attached to the Cortex-M3 system. These could include:
- External flash memory
- External RAM chips
- Memory-mapped LCD display
- Memory-mapped QSPI flash
Large flash memories are often mapped here to augment the internal flash size. Stack and data can also spill over into external RAM when needed. Display drivers and other peripherals also get mapped into this flexible region.
Private Peripheral Bus Region
The private peripheral bus occupies the top 256MB from 0xE0000000 to 0xEFFFFFFF. This region contains vital system control registers.
Key registers mapped here include:
- Nested Vectored Interrupt Controller (NVIC)
- System timer (SysTick)
- Memory Protection Unit (MPU)
- Debug control registers
The private peripheral bus region is access controlled to prevent corruption of critical system state information.
Default Memory Map
While the Cortex-M3 memory layout is flexible, most implementations follow a typical default mapping:
- 0x00000000 – 0x1FFFF: Internal flash memory (up to 128KB)
- 0x20000000 – 0x2000FFFF: On-chip SRAM (up to 64KB)
- 0x40000000 – 0x50000000: Peripheral region (up to 512MB)
- 0xE0000000 – 0xE00FFFFF: Private peripheral bus registers
Larger flash and RAM regions get appended after these initial mappings. The exact size and mapping is configurable via the processor’s memory protection unit.
Optimized for Embedded Systems
The Cortex-M3 memory layout balances performance and protection. Key features include:
- Unified memory map simplifies access
- Flash region write protects code
- SRAM region gives fast volatile storage
- Peripheral region enables memory-mapped control
- External region allows flexible memory expansion
- Private bus secures critical registers
These attributes make the Cortex-M3 memory architecture well-suited for embedded applications. The layout delivers an optimal combination of speed, determinism, and safety critical for ARM-based IoT devices.
