What are the operational modes of the Cortex-M3?

The Cortex-M3 processor from ARM has several operational modes that provide different levels of access and functionality. At the highest level, the Cortex-M3 has two main modes – Thread Mode and Handler Mode. Within Thread Mode, there are additionally Privileged and Unprivileged modes. Understanding these various operational modes is key to utilizing the capabilities of the Cortex-M3 processor effectively in embedded applications.

Thread Mode

Thread Mode is the main mode where most application threads and tasks run on the Cortex-M3 processor. This is where the actual application code executes. When the processor resets, it starts up in Thread Mode, specifically unprivileged Thread Mode.

Thread Mode provides access to the full Cortex-M3 instruction set and registers like R0-R12, SP, LR, PC, and xPSR. Exceptions and interrupts are enabled in Thread Mode so that the processor can respond to events and switch to Handler Mode as needed.

Privileged vs Unprivileged Thread Mode

Within Thread Mode, the Cortex-M3 makes a distinction between Privileged and Unprivileged states. This is determined by the least significant bit of the xPSR register, called the PRIMASK bit.

Unprivileged Thread Mode has the PRIMASK bit set to 1, meaning exceptions and interrupts are disabled. This prevents application threads from accidentally or intentionally modifying protected system resources. Most application code executes in unprivileged Thread Mode.

Privileged Thread Mode has the PRIMASK bit cleared to 0, enabling exceptions and interrupts. This allows threads running in this mode to access system level resources like setting interrupt priorities, external memory protection, system tick timer, and more. Privileged Thread Mode is used for operating system kernels, device drivers, and other system level code.

Handler Mode

Handler Mode is used to handle exceptions and interrupts. When an exception or interrupt occurs, the Cortex-M3 processor switches from Thread Mode to Handler Mode to run the corresponding exception handler or interrupt service routine (ISR). This allows the processor to deal with events and system issues without disrupting the main application threads.

The processor automatically switches back to Thread Mode once the handler or ISR completes. Handler Mode has access to the same Cortex-M3 registers and instruction set as Thread Mode, but with some differences:

• The Link Register (LR) is replaced with the Exception Link Register (EXC_RETURN) when switching to Handler Mode. This stores the return information to resume Thread Mode after handler completion.
• The Program Status Register is replaced with the Exception Program Status Register (xPSR). An extra bit indicates the exception number for identifying the source.
• The Stack Pointer (SP) is automatically switched to the Handler mode stack.
• Some instructions like sleep modes may be unavailable.

Together, these changes allow proper stacking and handling of exceptions/interrupts without corrupting the main thread’s context. Handler Mode also disables interrupts by default for atomic processing of events.

Exception Types

The Cortex-M3 processor supports the following types of exceptions that can trigger a switch to Handler Mode:

• Reset – Processor reset
• NMI – Non-maskable Interrupt
• HardFault – Serious error like bus fault or segmentation fault
• MemManage – Memory protection or MPU fault
• BusFault – Memory bus error
• UsageFault – Invalid instruction or illegal unaligned access
• SVCall – Supervisor call to OS kernel or supervisor
• DebugMonitor – Debug event triggered
• PendSV – Pendable request for system service
• SysTick – System tick timer interrupt
• IRQn – Configurable external interrupts

The first several exceptions are used internally by the Cortex-M3 for events like reset, faults, and debugger integration. SVCall, PendSV, and SysTick are used in most OS ports to provide supervisor calls, task switching, and scheduling. The IRQn external interrupts are configurable for handling device inputs like GPIO, ADC results, external peripherals, etc.

Switching Between Modes

The Cortex-M3 processor automatically switches from Thread Mode to Handler Mode when an exception or interrupt is triggered. This is controlled by a combination of hardware and the Nested Vectored Interrupt Controller (NVIC):

1. The interrupt input signal is detected and routed to the NVIC.
2. The NVIC determines if the interrupt is enabled and valid, using the Interrupt Control Register and priority settings.
3. If enabled, the NVIC signals the processor to switch to Handler Mode.
4. The processor finishes the current instruction, saves context to the stack, and enters Handler Mode.
5. The appropriate exception handler or ISR is looked up in the vector table and executed.

Once the handler completes, it executes the “BX LR” instruction to return to Thread Mode using the stacked return address in EXC_RETURN. This restores the main thread’s context and resumes execution.

The processor can also switch modes using software triggers like the SVC instruction to make a supervisor call in privileged Thread Mode. This causes the SVCall exception to enter Handler Mode and execute the supervisor/kernel subroutine.

In general, unprivileged Thread Mode cannot directly switch to other modes on its own. The exceptions, interrupts, and mode specific instructions provide a controlled mechanism to change modes securely.

Use Cases

Here are some typical use cases for the different Cortex-M3 operational modes:

• Unprivileged Thread Mode – Runs main application threads and tasks.
• Privileged Thread Mode – Device driver, OS kernel, and supervisor code.
• Handler Mode – Interrupt handlers, device drivers.
• Reset – Restart processor or application.
• NMI – Critical interrupts when main code bugs out.
• HardFault – Catch severe errors and faults.
• MemManage – MPU driver code to handle protection faults.
• BusFault – Bus error handling routine.
• UsageFault – Patch invalid instruction issues.
• DebugMonitor – Debugging integration code.
• SVCall – Makes requests to OS kernel.
• PendSV – OS context switching for task scheduling.
• SysTick – OS tick timer and interval handling.
• IRQn – External peripheral drivers.

By utilizing the different modes correctly, Cortex-M3 based applications can maintain robust performance, high reliability, and excellent responsiveness to events requiring attention from the main application threads.

Conclusion

In summary, the operational modes of the Cortex-M3 processor provide an efficient mechanism to separate application threads from system exception and interrupt handling. Thread Mode runs the main application and tasks, while Handler Mode deals with events. Privileged vs unprivileged states allow access control over system resources. Understanding how to leverage these modes allows designing robust and responsive embedded and real-time applications using the Cortex-M3.