ARM Cortex-M processors are designed for embedded applications requiring low power consumption and high performance. They are based on the ARMv7-M architecture and contain four major components: the processor core, the Nested Vectored Interrupt Controller (NVIC), the SysTick timer, and the Memory Protection Unit (MPU).
1. Processor Core
The processor core is the central processing unit that executes instructions and processes data. Cortex-M cores use the ARM Thumb instruction set which provides a balance of high code density and good performance. Some key features of Cortex-M cores:
- High efficiency 3-stage pipeline to achieve good performance at low clock speeds.
- ARMv7-M Thumb instruction set for optimal code density.
- Low power design with clock gating and power domains.
- Embedded trace macrocell (ETM) for instruction trace and profiling.
- Memory Protection Unit (MPU) for memory access control.
- Wake-up Interrupt Controller (WIC) for low power wake-up.
Popular Cortex-M processor cores include:
- Cortex-M0 – Ultra low power, low cost.
- Cortex-M0+ – Enhancements over M0 with slightly higher performance.
- Cortex-M1 – Obsolete, was meant for ASIC integration.
- Cortex-M3 – High performance with DSP extensions.
- Cortex-M4 – Adds single precision floating point unit.
- Cortex-M7 – Highest performance core with superscalar design.
- Cortex-M23 – Microcontroller profile optimized for cost sensitive IoT edge nodes.
- Cortex-M33 – Adds support for Armv8-M Security Extension.
The processor core executes the application software and interacts with other components via a system bus. It fetches instructions and data from memory, decodes instructions, executes them, accesses peripherals, and handles exceptions and interrupts.
2. Nested Vectored Interrupt Controller (NVIC)
The NVIC provides flexible and low latency handling of interrupts and exceptions in Cortex-M processors. Key features:
- Nested interrupt support – priorities and preemption.
- Reduced interrupt latency for fast response.
- Interrupt vectors can be located in Code memory for efficiency.
- Software triggered interrupts for inter-process communication.
- Standard and configurable exceptions like BusFault, MemFault etc.
- Wake-up Interrupt Controller (WIC) to handle interrupts during sleep mode.
The NVIC receives interrupt requests from various sources like peripherals, software exceptions and faults. Based on priority, it determines which exception should be handled by the processor core. This enables real-time response to critical events.
3. SysTick Timer
The SysTick timer provides a simple counter and interrupt generation capability. Key properties:
- 24-bit down counter clocked by the system clock.
- Configurable tick rate from 1 to 16 million ticks per second.
- Interrupt generation on counter reaching zero.
- Callback functionality to call software timer expiration handlers.
The SysTick timer can be used for creating periodic interrupts for time measurement, real-time task scheduling, and operating system tick events. It is commonly used in RTOS kernels.
4. Memory Protection Unit (MPU)
The MPU provides protection for memory regions to prevent unauthorized access. Useful capabilities:
- Up to 8 memory regions can be configured.
- Sub-region disable allows splitting regions into units of 32 bytes.
- Programmable region attributes like execute never, read-only, no access etc.
- Background and privilege attributes for unprivileged code access.
- Exported memory map for Debug and Trace subsystems.
The MPU allows creating separate memory domains for different processes and tasks. This prevents corruption of code and data in case of programming errors. It enables robust and secure embedded application design.
In summary, the four major components of Cortex-M processors are the processor core for executing software, the NVIC for interrupt handling, the SysTick timer for timekeeping, and the MPU for memory protection. Together they provide a rich set of features to enable high performance embedded application development.
