The Cortex-M processor family offers several debug interfaces that provide access to the core’s internal registers, memory, and peripherals for debugging and software development. The main debug interfaces available are SWD, JTAG, ETB, and DAP. Choosing the right interface depends on the capabilities required and constraints like cost and PCB area.
SWD Interface
The Serial Wire Debug (SWD) interface is the most commonly used debug interface on Cortex-M processors. It provides a two-pin bidirectional serial connection which gives the host debugger access to the core’s Debug Access Port (DAP). The DAP enables read and write access to core registers, memory, and peripherals. SWD uses just two pins – SWDIO for data and SWCLK for clock.
SWD supports complex debugging operations like halting the core, single stepping instructions, breakpoints, and watchpoints. It has good performance with clock speeds up to 50 MHz. SWD replaces the older JTAG interface and provides equivalent debug capability with fewer pins. All Cortex-M processors have built-in SWD. It is the standard debug interface used with Cortex debuggers and IDEs.
Advantages of SWD
- Only uses two pins
- High performance – up to 50 MHz clock
- Supports all debug operations like breakpoints
- Built-in to all Cortex-M cores
Disadvantages of SWD
- Not as widely supported as JTAG
- Requires target power to be on for debugging
- No boundary scan capability
JTAG Interface
The Joint Test Action Group (JTAG) interface was originally designed as a test interface for ICs and PCBs. It can also be used for debugger access on Cortex-M processors. JTAG uses 5 pins – TDI, TDO, TMS, TCK, and TRSTn. It works with a host debugger to shift serial data in and out to read and write to the core’s registers and memory.
JTAG supports all the standard debug operations like breakpoints, single stepping, and access to core registers. Since it has dedicated test pins, JTAG can be used to debug issues with a target board even if the processor is not running correctly. The downside is it requires 5 pins instead of just 2 for SWD.
Advantages of JTAG
- Widely supported standard
- Can debug board issues even if processor not running properly
- Supports boundary scan testing
Disadvantages of JTAG
- Requires 5 pins instead of 2
- Slower performance than SWD – up to 25 MHz
- Not built-in to all Cortex-M variants
ETB Interface
The Embedded Trace Buffer (ETB) is used to stream trace data from the Cortex-M processor to a debugger or host. It can capture detailed trace of program execution including timestamps, exceptions, function calls, etc. ETB uses a dedicated trace port with up to 8 pins depending on trace data width.
The trace data is stored in an on-chip RAM buffer before being transmitted to the host. ETB enables advanced debugging scenarios like profiling code execution to identify performance bottlenecks. Trace bandwidth is up to 320 Mbit/s. Trace port width options are 1, 2, 4, or 8 bit.
Advantages of ETB
- Captures detailed program execution trace
- Enables profiling and optimization
- Bandwidth up to 320 Mbit/s
Disadvantages of ETB
- Requires many dedicated pins – up to 8
- Trace buffer size is limited by on-chip RAM
- More complex to implement in software
DAP Interface
The Debug Access Port (DAP) is the debug control block inside Cortex-M processors. It handles the processor side of the SWD and JTAG debug connections. The DAP has several registers that can be accessed by the debugger to halt and control the processor core.
DAP registers include DP_CTRL to disable debug, AP_CTRL to access the memory access port, TARGETSEL to switch between debug targets, AP_IDR to identify the DAP, and more. DAP provides the low-level interface to the debug host. Both SWD and JTAG ports connect to the DAP module internally.
Key Functions of the DAP
- Debug link and port initialization
- Processor core halt/resume control
- Breakpoint and watchpoint management
- Access to core registers and memory through AP
- Target power sequencing
The DAP handles the critical debug functions needed to control and observe the processor. Upper level interfaces like SWD and JTAG communicate with the DAP to implement complex debugging operations.
Choosing Between Debug Interfaces
The choice between SWD, JTAG, ETB, and DAP depends on several factors:
- Capabilities needed – SWD or JTAG for basic debug, ETB for detailed trace
- Debug tool support – Some low cost tools may only support SWD
- Processor support – Older Cortex-M0/M1 parts lack SWD
- Board area and pins – SWD requires least pins and board space
- Target power requirements – JTAG can debug powered off target
- Performance needed – SWD faster than JTAG
For most modern Cortex-M development, SWD is the best choice. It provides full debug support with just two pins. JTAG is an option for legacy processor support or debugging powered off boards. ETB adds detailed tracing when profiling and optimization is needed. DAP is the internal interface accessed by SWD and JTAG.
SWD vs JTAG Summary
| SWD | JTAG | |
| Release | ARMv6 architecture | 1990 |
| Pins | 2 – SWDIO, SWCLK | 5 – TDI, TDO, TMS, TCK, TRSTn |
| Speed | Up to 50 MHz | Up to 25 MHz |
| Debug Capability | Full Cortex-M debug | Full Cortex-M debug |
| Processor Support | Cortex-M3 and beyond | All Cortex-M |
| Hardware Overhead | Minimal | Moderate |
| Boundary Scan | No | Yes |
Conclusion
ARM’s Cortex-M processors include a range of integrated debug interfaces. The most commonly used is SWD which offers full debug capability using just two pins. JTAG is an older standard that supports debug even if the target processor is not running. ETB provides trace functions for profiling and optimization. At the lowest level, the DAP module controls the debug functions.
Factors like debug capabilities required, tool support, processor compatibility, board area and cost determine the best choice. In most cases, SWD offers the best trade-off with modern tool and OS support. JTAG is an option for legacy boards or unusual debug scenarios. ETB adds value when tracing and profiling is needed. The DAP implements the debug logic internally on the Cortex-M processors.
