When exporting Cortex-M1 hardware platforms from Vivado to use in Vitis, users may encounter various issues that prevent the platform from being properly created. This can cause errors and problems when trying to build and run applications in Vitis using the exported platform. Some common Vitis issues with Cortex-M1 platforms exported from Vivado include:
Missing hwh file
One issue that can occur is that the .hwh hardware handoff file is missing from the exported platform. This file contains key information about the system hardware that Vitis needs to properly build and run applications. Without it, Vitis will not recognize the Cortex-M1 processor in the platform. To fix this, make sure the .hwh file is generated when exporting the platform in Vivado. The option to create the .hwh file is in the platform generator settings.
Incorrect MPU configuration
The Cortex-M1 processor has an optional memory protection unit (MPU). If the MPU is used, its regions and settings need to be correctly configured in the Vivado platform for proper operation in Vitis. Any mismatches between the hardware MPU config and the software MPU config exported to Vitis can cause memory access issues. Double check the address regions and access permissions match between Vivado and the exported platform.
Cache issues
Usage of the Cortex-M1 cache can also lead to issues if not properly configured between Vivado and Vitis. The cache settings in the exported platform must match the actual cache hardware implementation. Pay close attention to options like cache size, associativity, and latency. Incorrect cache configuration can lead to hard-to-debug errors in Vitis applications.
Memory map conflicts
If there are any overlaps or conflicts in the memory map between hardware IPs, the Cortex-M1 memory regions, and other address spaces, this can prevent the platform from being properly exported. Carefully review the memory map and make sure there are no overlapping addresses. Use address editor in Vivado to resolve any conflicts before exporting the platform.
XSA mismatch
The Cortex-M1 vector table offset and other exception settings are configured via the XSA (exception and abort control register). The XSA value exported from Vivado must match the actual hardware register value. If not, interrupts and exceptions will not work properly in Vitis. Verify the XSA value set in Vivado HW config matches the RTL/netlist.
Timing constraints missing
For hardware emulation and implementation, Vitis requires SDC timing constraints for the Cortex-M1 subsystem. If the exported platform does not contain .xdc timing constraint files, emulation and timing analysis will fail in Vitis. Use the write_xdc command in Vivado to generate the SDC constraints for the Cortex-M1 clock domain.
Incompatible tool versions
Vitis and Vivado need to have compatible version numbers to maintain platform compatibility. If Vivado and Vitis are too far out of sync, the Cortex-M1 platform created in Vivado may fail to work properly when imported into Vitis. Upgrade Vivado and Vitis to the latest compatible versions if you encounter version mismatch issues.
Incorrect compiler settings
The Cortex-M1 compiler settings exported from Vivado can sometimes be invalid or incompatible with Vitis. This can lead to build errors for platform projects in Vitis. Verify the compiler export settings and make sure the Cortex-M1 compiler version matches what is supported by Vitis for that platform.
Hardware debug problems
If the Cortex-M1 subsystem has on-chip hardware debug capability (ETB, ETM, etc), the debug module must be correctly instantiated and exported from Vivado for use in Vitis. Any issues with the debug module configuration can prevent hardware debugging from working properly in Vitis. Carefully check the debug module settings match between tools.
Peripheral connectivity issues
Any custom peripherals or IPs connected to the Cortex-M1 subsystem must have the proper ports exported to Vitis. Missing connections to key peripherals will prevent Vitis applications from working correctly. Review the Vivado block design and make sure all necessary AXI, AHB, or APB ports are correctly configured and exported.
Invalid clock configurations
The Cortex-M1 clock frequencies and clock relationships must be valid both in Vivado and in the exported Vitis platform. Any mismatch between the Vivado clocks/constraints and the Vitis clocks can cause timing issues. Double check that all Cortex-M1 clocks are properly defined and related in both tools.
Board part pin conflicts
For custom boards, conflicting pin assignments between Vivado board parts and the Vitis board parts can result in invalid XDC constraints or I/O issues. Review the board parts I/O ports in both tools and make sure the pin locations match for all exported interfaces.
Missing processor global timer
The Cortex-M1 global timer (systick) is required for correct operation of the FreeRTOS kernel and needs to be exported properly to Vitis. If the timer is missing or incorrectly configured, RTOS thread timing and scheduling will fail. Verify the Cortex-M1 processor’s global timer is present in the exported platform.
Incorrect reset configuration
Resets going into and out of the Cortex-M1 subsystem must be properly defined for Vitis platforms. Any reset naming, polarity, or connectivity differences between Vivado and Vitis can prevent correct reset operation. Check that processor resets match between tools.
Removing unused peripherals
It can help to remove any unused or unnecessary IPs from the Vivado block design before exporting the platform. Extra peripherals that are exported but not used by the application code take up resources in Vitis and increase complexity. Prune any unnecessary IPs to help optimize the platform.
Verifying address mappings
Much of the Cortex-M1 configuration involves address mappings for memory regions, peripherals, interrupts etc. Verifying these Vivado address mappings match the .dtb device tree contents in Vitis can help catch mismatches between tools. Fix any address mapping discrepancies before progressing too far.
These are some of the most common issues that can arise when exporting Cortex-M1 hardware platforms from Vivado into Vitis. Carefully validating the configuration, connectivity, and addresses on both sides can help avoid or troubleshoot any platform creation problems. Paying close attention to the hardware details during export is key to a smooth workflow between Vivado and Vitis.
