The Cortex-M0 DesignStart soft core provides a low-cost entry point for exploring ARM’s Cortex-M0 processor IP. By combining the DesignStart core with the MPS2+ FPGA development board, users can quickly prototype and evaluate Cortex-M0 based systems. This combination offers an affordable option for learning about ARM’s most energy efficient Cortex processor.
Overview of the Cortex-M0 DesignStart Core
The Cortex-M0 DesignStart core is a free soft core implementation of ARM’s Cortex-M0 processor. It is provided as synthesizable RTL code that targets low-cost FPGAs and CPLDs. The core is designed to enable fast prototyping and evaluation of the Cortex-M0 architecture.
Some key features of the Cortex-M0 DesignStart core include:
- Complete Cortex-M0 processor implementation with 3-stage pipeline
- Runs at up to 50 MHz in low-cost FPGAs
- Memory Protection Unit for software IP security
- Single cycle GPIO for efficient peripheral access
- Proven ARMv6-M Thumb instruction set architecture
By providing a zero-cost model, the DesignStart core allows students, hobbyists, and small companies to work with ARM’s industry leading Cortex-M processor IP. It enables hands-on experience with ARM’s tools and software ecosystem for prototyping Internet of Things and embedded applications.
Overview of the MPS2+ FPGA Board
The MPS2+ board from ARM is an FPGA development board designed specifically for use with the Cortex-M processor soft cores. It provides a ready-made platform for rapidly implementing prototype systems.
Key features of the MPS2+ board include:
- Xilinx Artix-7 FPGA (35T or 100T options)
- On-board DDR2 memory and flash storage
- Ethernet, USB host, audio interfaces
- General purpose I/O including buttons, LEDs, 7-seg displays
- Expansion header for custom peripheral modules
- JTAG/SWD debug interface
The MPS2+ provides everything needed to start developing on the Cortex-M0 soft core. It also integrates many common peripherals allowing for more complex system prototyping without requiring additional hardware.
Getting Started with the Cortex-M0 and MPS2+
Installing the Cortex-M0 DesignStart core on the MPS2+ involves a few key steps. The process can be easily completed in under an hour.
- Download the DesignStart IP-XACT files – These enable integration with Vivado.
- Install Vivado WebPACK – Xilinx’s free FPGA development toolkit.
- Generate the Vivado hardware project – Pull in the MPS2+ board files and Cortex-M0 core.
- Synthesize the design – Let Vivado compile the Verilog code for the target FPGA.
- Implement the design – Place and route the design for the FPGA’s resources.
- Generate the bitstream – Configure the FPGA with the Cortex-M0 implementation.
- Program the FPGA – Load the bitstream onto the MPS2+ via JTAG.
Once programmed, the Cortex-M0 core will be running on the FPGA. At this point, developers can start interacting with the processor using ARM’s software development tools. For example, the soft core can be debugged through Keil MDK or directly with gdb via an openOCD JTAG connection.
Example Software Projects
The Cortex-M0 and MPS2+ can be used to prototype a wide range of embedded software applications. Here are some example projects to help jump start development:
- Blinking LED – Classic embedded hello world using the MPS2+’s on-board LEDs.
- Interrupt handling – Example capturing interrupts from the timer and external buttons.
- ADC sampling – Reading analog values from potentiometers using the ADC interface.
- PWM control – Using pulse width modulation to dim LED brightness.
- UART communication – Sending/receiving data over the UART to a PC terminal.
- SPI peripheral – Communicating with a simple SPI based sensor.
These examples demonstrate using the Cortex-M0 peripherals and features like GPIO, timers, ADCs, PWM, UARTs, SPI etc. They can serve as templates for building more complex IoT prototypes.
Going Further with the Cortex-M0 and MPS2+
Beyond basic examples, the Cortex-M0 and MPS2+ can enable sophisticated embedded applications. Developers can leverage the available onboard peripherals or incorporate additional functionality using the FPGA fabric. Some possibilities include:
- Custom accelerators – Create dedicated hardware for performance critical operations.
- Co-processors – Offload specific tasks to run on separate cores.
- Video processing – Add a video decoder module for computer vision applications.
- Motor control – Implement complex control loops for robotics projects.
- Sensor fusion – Aggregate data from multiple real-time sensor sources.
With its reprogrammable logic, the MPS2+ lets developers customize and extend the system to their needs. Complex FPGA-based peripherals can be controlled directly from the Cortex-M0 core. This enables advanced prototyping of embedded and IoT designs.
Conclusion
The Cortex-M0 DesignStart core and MPS2+ FPGA board provide an accessible development platform for exploring ARM’s low power processor IP. With the free soft core and affordable hardware, engineers can gain hands-on experience building prototypes with the Cortex-M0 architecture. As a result, this combination offers an excellent way to learn about designing ARM-based embedded and IoT applications.
