Using External BRAM as Instruction/Data Memory for Cortex-M1

The Cortex-M1 processor allows for flexible memory configuration by supporting both internal and external memories for instructions and data. Using external block RAM (BRAM) as additional instruction and data memory can provide several benefits compared to relying solely on internal SRAM, such as increased memory size, lower cost per bit, and reduced power consumption.

Benefits of Using External BRAM

Here are some of the key benefits of using external BRAM with Cortex-M1:

• Increased memory size – Internal SRAM is limited, often to just 32-128KB. External BRAM can provide megabytes of additional memory.
• Lower cost per bit – External BRAM in an FPGA or ASIC is less expensive than large internal SRAM.
• Reduced power consumption – Large internal SRAM arrays consume more leakage and active power than external memory.
• Flexibility – External memory size and organization can be customized for each design.
• High performance – Fast block RAM access times reduce wait states versus external DRAM or flash.

Cortex-M1 Memory Interface

The Cortex-M1 supports up to 4 memory regions – one each for instruction and data, and two optional regions. Each region can be configured to interface with internal SRAM or external memories.

For external memory interfaces, the Cortex-M1 memory controller provides support for asynchronous memories like SRAM and synchronous memories like SDRAM. The associated register interface allows for configuring wait states, endianness, and other options.

To use external BRAM, the memory controller must be configured appropriately to match the BRAM port width and latency. The timing diagrams in the Cortex-M1 TRM provide the necessary timing requirements.

Instruction Memory Configuration

To use external BRAM for instruction memory, the following steps are typically followed:

1. Instantiate BRAM block(s) in the FPGA or ASIC memory subsystem.
2. Configure the Cortex-M1 MEMMAP register to point the ICode bus to the external memory controller.
3. Connect the ICode bus to the BRAM port(s).
4. Configure BRAM latency to match Cortex-M1 fetch timing.
5. Set the IRSIZE bit in MEMMAP to the BRAM port width.
6. Program wait states in the MEMCTRL register to satisfy BRAM latency.

If the instructions cross BRAM block boundaries, MMU configuration may be needed to present a unified address space. The design should ensure BRAM contents are initialized before code execution.

Data Memory Configuration

Using external BRAM for data memory follows a similar process:

1. Instantiate BRAM block(s).
2. Connect DCode bus to BRAM port(s).
3. Configure BRAM latency.
4. Set DRSIZE bit in MEMMAP to match port width.
5. Set wait states to satisfy BRAM latency.
6. Configure MMU if data crosses BRAM blocks.

The processor automatically handles endianness based on the MEMCTRL register configuration for external accesses. For data, initialization is not required before execution.

Dual Instruction and Data Memory

For maximum flexibility, the Cortex-M1 design can utilize both internal SRAM and external BRAM simultaneously. For example:

• Small internal SRAM for critical code and data.
• Large external BRAM for bulk storage.

This dual scheme provides low latency access for key functions in SRAM along with the capacity benefits of BRAM. The MMU allows seamless accesses between the two memory spaces.

Memory Configuration Guidelines

Following some general guidelines can help optimize the memory configuration:

• Allocate heavily used code and data to internal SRAM for lowest latency.
• Place bulk code and data in external BRAM to maximize capacity.
• Use single-cycle latency BRAM if possible.
• Minimize wait states to reduce stalls.
• Use MMU to create a unified address space.
• Separate instruction and data memory for bandwidth.

Other External Memory Options

In addition to BRAM, the Cortex-M1 can also utilize external parallel SRAM, flash, and SDRAM memories. However, BRAM provides an optimal blend of density, bandwidth, low latency, and simple interfacing. Parallel SRAM offers similar benefits but is less cost effective for larger sizes. SDRAM provides high capacity but requires complex controllers to manage.

Conclusion

Using external BRAM for Cortex-M1 instruction and data memory offers increased capacity without sacrificing performance. Careful configuration of the memory regions, port connections, wait states, and MMU ensures correct functional operation. Following guidelines for allocating critical and bulk memory optimizes the overall system. BRAM offers an attractive memory solution for both ASIC and FPGA based Cortex-M1 designs.