The Cortex-M1 processor supports instruction fetch from external flash memory. This allows for larger and more complex programs to be run than would fit in the processor’s internal flash memory. Setting up external flash requires configuring the memory interface and ensuring the instruction fetch mechanism can access the external memory correctly.
Overview of Cortex-M1 Instruction Fetch
The Cortex-M1 processor contains internal flash memory for storing program instructions. However, this memory is limited in size. For larger programs, the processor can fetch instructions from external flash memory connected to its external memory interface.
Fetching instructions from external flash requires the memory interface to be configured correctly. The external flash must be mapped into the memory space so that instruction fetches can access it. Any wait states or other access delays must be configured to ensure reliable instruction fetch.
The processor uses a prefetch unit to speculatively fetch instructions ahead of time. This helps improve performance when executing sequentially. The prefetch unit must be aware of any external flash access delays to function properly.
Fetching instructions from slower external flash can impact performance compared to internal flash. The processor may need to wait for instructions, potentially stalling execution. Code and data should be arranged appropriately to minimize impacts.
Connecting External Flash to the Cortex-M1
The Cortex-M1 memory interface provides access to external memories. It includes a bus matrix that connects to the processor core, peripherals, and external ports. The external flash must be connected to one of the ports.
Typical connections use the higher-bandwidth AHB ports. These provide 32-bit access suitable for fetching instructions. Lower bandwidth APB ports can also be used but may impact performance.
The external flash chip connects to the processor using standard buses like AHB or APB. The data sheet for the specific flash chip provides details on electrical connections and interfaces. Pay close attention to any specific timing requirements.
The memory interface operates at a particular clock frequency. Ensure the external flash supports this frequency. Adding wait states may be necessary to account for interface timing constraints.
For improved performance, consider using higher speed “zero-wait state” external flash. This avoids fetch delays associated with slower flash chips.
Configuring the External Flash Memory Map
For the processor to access instructions from external flash, it must be mapped into the memory address space appropriately. This is configured via the memory interface mapping registers.
The external flash should be mapped into the space expected for instruction fetches. This is typically done from address 0x00000000 on up. Peripherals, I/O, and data can be mapped into other regions.
Take care that the full external flash capacity fits within the mapped address range. Attempting to fetch instructions from unmapped addresses will cause bus faults or errors.
It may be desirable to map internal and external flash contiguously. For example, internal flash from 0x00000000 to 0x0003FFFF and external continuing at 0x00040000. This allows code to span both seemlessly.
Mapping external flash cacheable can improve performance. The processor can cache fetched instructions and data in its instruction or data caches.
Configuring Wait States
External flash may require wait states during access to meet timing requirements. These must be configured correctly in the memory interface or instruction fetches may fail.
Check the external flash datasheet for required wait states. Typically between 0-3 wait states for each access depending on the operating frequency.
Wait states are added by configuring a register in the memory interface controller. Take care to add wait states only to the interface connected to external flash.
Too many wait states penalize performance unnecessarily. Too few may result in unreliable operation. The number of wait states required can vary if using a frequency other than the external flash rating.
Initializing the Prefetch Unit
The Cortex-M1 processor uses a prefetch unit to speculatively fetch instructions ahead of time when executing sequential code. This improves performance by hiding fetch latency.
For the prefetch unit to function optimally, it must be configured with information on the instruction memory system, including any wait states.
A prefetch initialization routine runs early in the program startup code. It configures parameters like the memory interface timing and number of wait states.
Well tuned prefetch settings improve performance when executing from external flash. Poorly configured, it may still attempt to run ahead and issue faulty speculative fetches.
Issues and Optimizations
Fetching instructions from external flash can encounter issues that impact performance. Careful design choices can help optimize the system.
The Cortex-M1 usually fetches sequential instructions in chunks for efficiency. Branches or other control flow changes can cause stalls while it begins fetching from the new location.
Within the code, place critical loops and functions in internal flash whenever possible. Fetching from here avoids the latency impacts of external flash.
Interleaving code and data in external flash results in frequent switching between instruction and data accesses. A separate data flash device avoids this.
Some external flashes support “execute in place” which allows direct code execution. Otherwise, code must usually be copied into internal RAM before execution.
Example Initialization Code
Below is sample code that performs a basic configuration of external flash for instruction fetch on a Cortex-M1 processor. It maps the flash memory range, configures wait states, and initializes the prefetch unit. // Map external flash from 0x00000000 to 0x00FFFFFF MEMMAP = 0x00000000; // Configure 3 wait states on external flash memory interface FLASH_INTERFACE_SETUP = 0x00000003; // Initialize prefetch unit PREFETCH_SETUP = 0x00000001; PREFETCH_ENABLE = 1; // Copy application code from external to internal flash CopyCode(); // Jump to application entry point JumpToApp();
This illustrates the typical steps involved in setting up external flash for instruction fetch. Actual code would need to be tailored for the specific system flash architecture and memory map.
Conclusion
The Cortex-M1 processor can support larger and more complex application code by fetching instructions from external flash. Correctly configuring the memory interfaces, wait states, and prefetch operation ensures reliable instruction delivery.
Careful partitioning of code between external and internal flash along with well-structured software design can help mitigate the impacts of slower external memory. With these considerations, the Cortex-M1 instruction fetch mechanism provides flexible support for a wide variety of application requirements.
