The Cortex-M4 processor, like most modern processors, supports power-down modes to conserve energy when the system is idle. To properly resume from a low-power state, the processor’s context (register contents, stack pointer, program counter, etc.) must be preserved. This article provides an overview of the different low-power modes, reset behavior, and how to save and restore processor state to enable low-power operation.
Cortex-M4 Low Power Modes
The Cortex-M4 supports several low-power modes with different wake-up latencies and energy savings:
- Sleep Mode: CPU is stopped, peripherals continue operating. Wake-up latency is fast.
- Deep Sleep Mode: CPU and most peripherals are powered down. Only low-power peripherals can operate. Wake-up latency is moderate.
- Standby Mode: The processor and all peripherals are powered down. Only low-power clocks are active. Wake-up latency is slow.
In all cases, the processor’s context needs to be preserved over the low-power state. The wake-up event (interrupt, reset, etc) will cause the processor to resume where it left off.
Reset Behavior
When the Cortex-M4 wakes from a low-power state, it will undergo a reset sequence. The reset behavior depends on the reset source:
- Power-on Reset: Occurs when power is first applied. Resets all registers and memory.
- External Reset: Triggered by external reset signal. Resets most registers and memory.
- Wake-up Reset: Caused by wake-up from standby mode. Minimal reset of core registers.
For wake-up resets, the processor restores much of the core register state (stack pointer, program counter, etc.) from special reset values configured prior to power-down. However, some application register contents and memory will be lost.
Saving Processor Context
To preserve the complete processor state, the application must save critical processor values to a safe memory location before power-down and restore them after wake-up. This includes:
- General purpose registers (R0-R12)
- Stack pointer (PSP)
- Link register (LR)
- Program counter (PC)
- Priority mask registers
- Control register contents
The processor context can be saved to internal SRAM, external RAM, or non-volatile storage if available. For example: /* Save processor context */ // Stack frame for context saving PUSH {R4-R11} // Save remaining regs MOV R0, SP MOV R1, LR MOV R2, PSP // Save regs to external SRAM STR R0, [sram_base, #0] STR R1, [sram_base, #4] STR R2, [sram_base, #8] // Save PRIMASK, FAULTMASK, BASEPRI MRS R0, PRIMASK MRS R1, FAULTMASK MRS R2, BASEPRI STR R0, [sram_base, #12] STR R1, [sram_base, #16] STR R2, [sram_base, #20] // Save remaining core registers …
The processor context is commonly saved within an interrupt handler, before triggering the low-power mode. The wake-up event will trigger a new interrupt which can then restore the context.
Restoring Processor Context
On wake-up, the application must restore the saved processor state before resuming normal operation. This is commonly done in the interrupt handler triggered by the wake-up event. For example: /* Restore processor context */ // Restore core registers LDR R0, [sram_base, #0] LDR R1, [sram_base, #4] LDR R2, [sram_base, #8] MSR PSP, R2 MOV LR, R1 MOV SP, R0 LDR R0, [sram_base, #12] LDR R1, [sram_base, #16] LDR R2, [sram_base, #20] MSR PRIMASK, R0 MSR FAULTMASK, R1 MSR BASEPRI, R2 // Restore additional registers …
Once the context has been restored, the wake-up handler returns to the point where the processor originally suspended operation. The application continues running normally.
Low Power Library Assistance
Manually saving and restoring the processor context requires meticulous programming. Many Cortex-M vendors provide aLow Power Library (LPM) to simplify low-power programming. The LPM API typically allows entering and exiting low power modes without dealing directly with register saving.
For example, to enter standby mode: LPM_SetPowerMode(LPM_PowerMode_Standby); LPM_EnterLowPower();
The LPM library handles saving context, triggering power-down, managing wake-up, and restoring context automatically. This simplifies low-power programming.
Debug Considerations
When debugging low-power code, the debugger connection will be temporarily lost during power-down. Debugging options include:
- Single stepping to confirm context is saved before power-down.
- Setting debugger to halt at wake-up before context restore.
- Monitoring power modes using debug I/O or instrumentation.
Special debug configurations may be needed to reconnect and restore debugger operation after wake-up.
Conclusion
The Cortex-M4 supports flexible power-down options for power savings. Preserving the processor state enables seamless resume operation after wake-up. Manually saving processor context requires careful programming. LPM libraries simplify the process but debugging may require special configurations. With careful design, Cortex-M4 power modes can be leveraged for substantial energy savings.
