The Cortex M0 is an ultra low power 32-bit microcontroller developed by ARM Holdings. It is aimed at embedded applications that require minimal power consumption and high performance in a small physical footprint. The Cortex M0 achieves this through an efficient 3-stage pipeline, low latency interrupt handling, and extensive clock gating. In this article, we will take a detailed look at the pinout and peripherals available on the Cortex M0 microcontroller.
Power Pins
The Cortex M0 requires a 1.8V power supply for the core logic and a 3.3V supply for the I/O pins. There are separate pins for each power domain:
- VDD – This is the 1.8V power supply pin for the core logic.
- VDDA – This is the 3.3V power supply for the I/O pins.
- VSS – This is the ground reference for the core logic.
- VSSA – This is the ground reference for the I/O pins.
Proper decoupling capacitors need to be provided between VDD/VSS and VDDA/VSSA to stabilize the power rails from noise and transients. Typically 0.1uF ceramic capacitors are used for decoupling.
Clock Pins
The clock signals for the Cortex M0 are provided through dedicated pins:
- XTAL1 – Input clock from an external crystal oscillator.
- XTAL2 – Output clock to an external crystal oscillator.
- EXTCLK – Optional external clock input for bypassing the internal PLL.
The Cortex M0 has an internal PLL that can multiply the external clock frequency up to 50MHz. Bypassing the PLL using the EXTCLK pin disables the PLL to reduce power consumption in low clock frequency applications.
Reset Pins
The Cortex M0 has two reset inputs for flexibility:
- nRESET – Active low reset signal that resets the whole microcontroller.
- RESET_NMI – Active low reset signal that triggers the non-maskable interrupt (NMI) for debug/diagnostic use.
The nRESET pin is the one typically connected to a reset button or power-on reset circuitry. The RESET_NMI option allows a reset event to be handled by NMI firmware routines instead of a full reset in some debug scenarios.
Debug Pins
For debugging and programming, the Cortex M0 provides a standard ARM 2-wire debug interface:
- SWCLK – Serial wire clock signal that clocks data during debug access.
- SWDIO – Bidirectional serial wire data I/O signal for debug access and programming.
In addition, there are several dedicated pins for debug/trace functionality:
- TRACECLK – Dedicated trace clock output for timing trace data.
- TRACEDATA[3:0] – 4-bit trace data bus with packet information.
- TRACECTL – Trace control signal to enable trace packets.
System Pins
The Cortex M0 provides some dedicated pins for system-level functions:
- SLEEPDEEP – Input signal to select between sleep or deep sleep low power modes.
- WICENACK – Output acknowledge signal for waking up from deep sleep mode.
- SYSRESETREQ – Output to request a system reset.
These signals allow system-level management of low power modes and coordinate reset across multiple devices or power domains.
Peripheral Interfaces
The Cortex M0 peripheral set consists of basic interfaces like GPIO, timers, serial, ADC, etc. The exact peripheral mix depends on the specific M0 chip being used. Here are some of the common peripherals available:
GPIO
Up to 32 GPIO pins are available in the Cortex M0 design. Each GPIO can be individually configured for input or output operation, with options like pull-up/down, drive strength, and open drain mode. Interrupts can be triggered on GPIO state changes.
Timers
Up to 4 general purpose 16-bit timers are provided, each with up to 6 capture/compare channels. The timers have functions like input capture, output compare, PWM generation, count-up, count-down, and more. Interrupts can be configured on timer overflow, capture events, or compare match.
Serial
Up to 4 serial interfaces are available, configurable as either SPI, I2C or UART. SPI mode supports up to 2 chip selects. I2C mode supports standard and fast mode operation. UART mode supports standard baud rates up to 2.5Mbps, with options like LIN bus support, smartcard mode, and more.
ADC
A 10-bit Successive Approximation Register (SAR) ADC is provided with up to 16 input channels. The ADC supports single shot and continuous conversion with wait states configurable between each sample. ADC data can be left or right aligned. An interrupt can be triggered when conversions are complete.
DAC
Some Cortex M0 variants include a DAC module with 1 or 2 channels. Each DAC channel is a 10-bit voltage output DAC that can operate in 8-bit mode if desired. Continuous mode and sample/hold modes are supported.
Comparator
A 2-input analog comparator is included, which compares the voltages on its positive and negative inputs. The output can be polled or can trigger an interrupt on state changes. Inputs can be internally connected to the DAC or ADC outputs.
RTC
A real-time clock module with dedicated 32kHz clock input allows keeps track of time and date information, even in low power modes when the system clock is disabled. Calendar functions like day/month are supported.
Package Options
The Cortex M0 is available in a variety of compact surface mount package options. Common options include:
- VQFN32 – 32-pin 5mm x 5mm quad flat no-leads package
- LQFP48 – 48-pin 7mm x 7mm low profile quad flat package
- LQFP64 – 64-pin 10mm x 10mm low profile quad flat package
- UFBGA64 – 64-pin 5mm x 5mm ultra fine pitch ball grid array
The smaller VQFN32 option is popular for space-constrained and wearable applications. The LQFP options provide good balance of size and ease of PCB assembly. UFBGA provides a very compact footprint but requires specialized assembly considerations.
Summary
The Cortex M0 provides a versatile mix of low power consumption, good performance, and small physical size. The pinout enables all the necessary functions through a set of power, clock, debug, system, and peripheral interface pins. A wide range of package options makes it suitable for demanding embedded applications.
With its pinout carefully optimized for embedded use, the Cortex M0 microcontroller provides an excellent foundation for Internet of Things edge nodes, wearable electronics, sensor hub applications, and other spatially constrained embedded designs.
