Managing Reset Domains in Cortex-M3 Systems

The Cortex-M3 processor contains multiple reset domains that allow independent reset control of different modules within the system. Proper configuration and management of these reset domains is crucial for developing robust and reliable Cortex-M3 based systems.

Introduction to Reset Domains

A reset domain refers to a logical grouping of modules that share common reset control signals. The Cortex-M3 contains several reset domains, including:

• System reset domain – Includes the processor core, Nested Vectored Interrupt Controller (NVIC), Flash memory interface, and debug components.
• Peripheral reset domain – Includes peripherals like timers, ADC, IO ports, etc.
• Backup reset domain – Includes the backup registers and RTC module.

Each reset domain can be reset independently via dedicated reset control signals. This allows selective resetting of modules without impacting other unrelated modules. Key benefits of having multiple reset domains include:

• Improved reliability – Critical system modules can remain operational if another module needs to be reset.
• Easier software development – Software bugs can be recovered by resetting the affected modules only.
• Flexibility – Modules not actively used can be held in reset to save power.

Proper configuration of the reset architecture is required to utilize these benefits fully. The reset sources, mapping of modules to domains, reset sequencing, etc. need to be set correctly.

Reset Sources

The Cortex-M3 processor supports several reset sources that can initiate a system reset:

• Power-on reset – Generated at system power-up to ensure all modules start in a known state.
• External reset pin – Allows an external reset signal to reset the system for recovery from errors.
• Software system reset – Executing the SYSRESETREQ instruction causes a system reset.
• Watchdog reset – The watchdog timer can reset the system if not periodically refreshed by software.

These reset sources by default initiate a full system reset, affecting all modules. However, most reset sources can be configured to target specific reset domains only:

• The external reset pin can be configured to reset the system domain only.
• Watchdog reset can target the system domain or peripheral domain.
• Software reset instruction can target the system, peripherals, or both.

This selective reset capability allows recovery from errors without a full system reboot.

Mapping Modules to Reset Domains

The processor includes several peripherals like timers, ADC, USB, etc. Each peripheral needs to be mapped to one of the reset domains.

Most peripherals are connected to the peripheral reset domain by default. However, some peripherals like system timers, watchdog, and the memory/bus interfaces are connected to the system reset domain. This ensures core system functionality remains available even if the peripheral domain is held in reset.

Here are some guidelines for mapping modules to reset domains:

• Group critical system modules under the system domain for better reliability.
• Assign modules not actively used to the peripheral domain, which can be held in reset to save power.
• Assign modules that may need individual resets to the peripheral domain.
• Minimize the number of modules in the system domain to limit the impact of system resets.

The processor configuration tool allows configuring the reset domain mapping as per the system requirements.

Reset Sequencing

The order in which different reset domains are reset, referred to as reset sequencing, is important to avoid issues:

• The system domain must be reset first to ensure all system logic is reset before peripherals.
• The backup domain should be reset last to avoid data loss from the backup registers.
• Adequate delay must be provided between resetting domains to allow logic to stabilize.

A typical reset sequence would be:

1. Assert system reset and hold for minimum duration.
2. Assert peripheral reset and hold for minimum duration.
3. Release system reset.
4. Release peripheral reset.
5. Assert backup reset and hold for minimum duration.
6. Release backup reset.

The reset control logic handles this sequencing automatically based on the programmed delay parameters. The delays should be set appropriately based on the system design.

Configuring Reset Behavior

In addition to the reset sequencing, the following reset-related behaviors can be configured:

• Reset sources – Configure which sources can trigger system vs peripheral vs backup reset.
• Reset vectors – Separate reset vectors for system and backup domains.
• Reset duration – Minimum pulse width for retaining modules in reset.
• Reset masks – Allows selectively enabling resets from different sources.

These configurations are done through a set of control registers present in the reset control block of the processor. The processor configuration tool can be used to generate the register initialization values.

Debug Considerations

Use of the processor’s debug/breakpoint features can impact reset behavior:

• Debug halt prevents reset, so stalled code execution may prevent reset.
• Debug breakpoints use the system reset domain, so frequent breakpoint hits can impact reset.
• Debug logic is itself sensitive to glitches on resets.

Guidelines for using debug/reset features:

• Minimize resets while code executes in debug halt.
• Reduce breakpoint usage during development.
• Ensure proper sequencing between debug enables and resets.
• Disable debug during production code to avoid issues.

Reset Domain Use Cases

Some examples of selectively utilizing reset domains in system design:

Recovery from Peripheral Crashes

Issues in peripherals like DMA, USB, etc. can lead to system hangs or crashes. By mapping these peripherals to the peripheral reset domain, they can be reset to recover without full system reboot.

Error Handling with Watchdog Reset

The watchdog timer can be configured to reset the system domain on software failures. The system reset handler can then analyze errors and selectively clear peripherals domains for recovery.

Low Power Mode with Partial Resets

When entering low power mode, unused peripherals mapped to the peripheral reset domain can be held in reset. This prevents them from drawing power until re-enabled by software.

Fallback Boot with Backup Register

A backup register loaded by bootloader can indicate if main app boot failed. On reset, bootloader can check this register and load fallback image if needed, before releasing backup reset.

Remote System Recovery

For remotely managed systems, external reset pin can be controlled to reset the system domain remotely. Allows recovery without physical access.

Reset Configuration in Software

In addition to hardware configuration via processor configuration tool, software must initialize reset domains correctly during boot:

• Load reset control registers with desired reset configuration.
• Setup reset source interrupts and handlers as needed.
• Initialize watchdog timer and kick it periodically if used.
• Setup handlers for system and backup reset vectors.
• Clear any pending reset statuses at boot.

Software should also contain mechanisms to recover from and log resets events when they occur.

Conclusion

The Cortex-M3 reset architecture with multiple domains provides a powerful capability for system robustness. Proper configuration and management of reset domains, sequencing, sources, and recovery mechanisms in both hardware and software are essential for leveraging this in system design.