Incorrect Code Generation by GNU-ARM Compiler for Cortex-M0/M0+/M1

The GNU Arm Embedded Toolchain, also known as GNU Tools for Arm Embedded Processors, is a suite of open source software development tools for creating software for Arm Cortex-M and Cortex-R family processors. It includes the Arm Embedded GCC compiler, linker, assembler, and other tools needed to build software for these devices. However, some users have reported issues with incorrect code generation when using the GNU Arm compiler (arm-none-eabi-gcc) for Cortex-M0/M0+/M1 chips.

The Issue of Incorrect Code on Cortex-M0/M0+/M1

Specifically, the compiler may generate incorrect code when optimizing for these Cortex-M profiles, leading to subtle and difficult-to-debug errors in some cases. Some of the key problems that have been reported include:

• Incorrectly optimizing away “redundant” instructions leading to incorrect program behavior
• Generating incorrect instruction sequences for some multi-byte operations
• Mishandling of some Interrupt Service Routines (ISRs)
• Incorrect alignment of stack variables

These types of code generation issues are particularly problematic because they result in assembler code that seems valid but executes incorrectly on the target processor. This leads to hard-to-diagnose runtime errors. The problems seem to be most pronounced when using higher levels of optimization such as -O2 or -Os, but can sometimes happen even at -O1 or with no optimization at all.

Examining Specific Cases of Code Generation Bugs

Let’s look at some specific examples reported in GCC bug trackers and discussion forums to understand exactly what types of incorrect code generation failures have been observed on Cortex-M0/M0+/M1:

Incorrectly Removing “Redundant” Instructions

One of the most common issues reported is that the compiler will incorrectly optimize away instructions it deems redundant or unnecessary, but which are actually required for correct program execution. For example:

uint32_t x = do_something(); 

x &= 0xFF; // keep lower 8 bits

do_something_else(x);

Here the compiler may optimize away the “&= 0xFF” instruction since the lower 8 bits of x are not used subsequently. However, this instruction may be essential for correctness if do_something() returns values where only the lower 8 bits are valid.

Incorrect Multi-byte Instruction Sequences

The compiler may also generate incorrect Thumb or Thumb-2 instruction sequences for certain multi-byte operations. For example:

int16_t a, b;
int32_t c;

c = a * b;

The compiler may compute this multiply incorrectly by generating a 2-instruction sequence that does not properly handle potential overflows or carries.

Buggy Interrupt Service Routines

There also seem to be issues with how the compiler handles interrupts and interrupt service routines (ISRs) in some cases. For example, it may fail to properly save/restore registers in ISRs according to the Cortex-M ABI standards.

Incorrect Stack Variable Alignment

Some users have also reported issues with alignment of stack variables being incorrect in some code compiled for the Cortex-M0/M0+/M1 profile leading to hard faults or other runtime crashes.

Probable Root Causes of These Code Generation Issues

While the specifics vary for each type of code generation failure, most stem from compiler deficiencies in one or more of these areas when targeting Cortex-M0/M0+/M1:

• Incorrect assumptions about instructions or capabilities of the target CPU profile
• Problematic optimizations passes that fail to consider instruction side effects
• Insufficient testing of compiler output against real hardware
• Lack of safeguards against optimizations that violate C semantics

In essence, the compiler makes invalid optimizations or code generation decisions based on assumptions that do not hold for these Cortex-M profiles. Compounding this is lack of testing on real low-end Cortex-M hardware that would catch these issues.

Steps to Take for Affected Developers

If you are developing software for Cortex-M0/M0+/M1 using the GNU ARM compiler and run into issues with incorrect code generation, here are some steps to take:

1. Try disabling optimizations completely using -O0 and see if the issues persist. This may point to a bug triggered by higher optimization levels.
2. Isolate a small reproducible code sample demonstrating the issue.
3. File a bug report with this sample on the GCC bug tracker and on Arm’s developer forums.
4. Consider using glimpses of inline assembly or intrinsics where needed to work around incorrect code generation.
5. Evaluate other compiler options like -mno-thumb-interwork which may avoid some incorrect code.
6. For critical code sections, inspect the generated assembly and confirm it matches expectations.

While not ideal, these steps can help minimize and diagnose problems with incorrect code generation by the GCC ARM compiler for Cortex-M0/M0+/M1 targets.

Future Outlook on These Issues

Incorrect code generation issues specifically affecting Cortex-M0/M0+/M1 appear to be an ongoing challenge with GCC ARM. While some improvements have been made in recent GCC versions, problems still persist especially when using optimizations.

However, Arm and the GCC community are aware of these deficiencies and are working to improve the compiler, for example by:

• Enhancing compiler testing on Cortex-M hardware.
• Adding CPU specific safeguards around problematic optimizations.
• Improving the compiler’s internal model of the Cortex-M0/M0+/M1.
• Increasing developer awareness of known codegen bugs.

So while workarounds are needed today, future GCC releases should continue to reduce the occurrence of incorrect code generation on these microcontroller targets.